MM6108-MF08651-US Data Sheet
DS102
1 Product Overview
1.1 Introduction
Morse Micro provides a complete Wi-Fi HaLow connectivity solution. The MM6108-MF08651-US is a fully integrated Wi-Fi HaLow® module featuring the MM6108 Wi-Fi HaLow SoC. It offers long-range, low-power consumption, and superior RF performance.
The MM6108-MF08651-US module is designed in compliance with the IEEE 802.11ah standard. It supports data rates up to 32.5 Mbps and has programmable operation between 902 MHz and 928 MHz.
This module includes an ultra-long-reach PA, a high linearity LNA, a SAW filter, a T/R switch, and a 32 MHz crystal oscillator. It has been designed for a simplified Wi-Fi HaLow connection to an external host for applications where customers want to replace their prior RF technology with a Wi-Fi HaLow connection while using the latest WPA3 security protocol.
Battery-operated applications are supported by a combination of features inherently supported by the module. The IEEE 802.11ah standard provides extended sleep times for battery-operated stations (STAs or client devices), with longer durations than other prior IEEE 802.11a/b/g/n/ac generations. The standard also allows longer extended maximum idle times for clients to conserve energy without being removed from the access point’s (AP’s) list of associated devices.
1.2 Features
Ultra-long-range, low-power Wi-Fi HaLow module for IoT applications:
Channel bandwidth options of 1/2/4/8 MHz
Single-stream max. data rate of 32.5 Mbps @ 8 MHz or 15 Mbps @ 4 MHz channel
Radio supporting Sub-1 GHz frequency bands
Frequency range: 902-928 MHz
Max output power: 24.5 dBm
802.11ah OFDM PHY supporting WFA HaLow certification
BPSK & QPSK, 16-QAM & 64-QAM Modulation
Automatic frequency and gain control
Packet detect and channel equalization
Forward Error Correction (FEC) coding and decoding
Support for Modulation and Coding Scheme (MCS) rates MCS 0-7 and MCS 10
Support for 1 MHz and 2 MHz duplicate modes
Support for Traveling Pilots and Short Guard Intervals
802.11ah MAC supporting WFA HaLow certification
Support for STA and AP roles
Listen-Before-Talk (LBT) access with energy detect
802.11 power save
802.11 fragmentation and defragmentation
Packet aggregation
Power-Saving Target Wake Time (TWT) support for long battery life
Restricted Access Window (RAW)
Automatic and manual MCS rate selection
Support for various interface options
SDIO 2.0 compliant host/slave interface
2 x UARTs
Power Management Unit (PMU) for various modes of operation
Power-down (interrupt driven wake)
Hibernate mode (internal / external wake)
Active receive / transmit mode
Integrated DC-DC converter supporting a voltage supply from 3.0V to 3.6V
Wide spectrum of security features
AES encryption engine
Hardware support for SHA1 and SHA2 hash functions (SHA-256, SHA-384, SHA-512)
WPA3 including Protected Management Frames (PMF)
Opportunistic Wireless Encryption (OWE)
1.3 Applications
The MM6108-MF08651-US is ideally suited for Internet of Things (IoT) and Machine-to-Machine (M2M) applications such as:
Surveillance cameras and sensors
Cloud connectivity
Low-power sensor networks
Building Automation Systems (BAS)
Asset tracking and management
Machine performance monitors and sensors
Building access control and security
Drone video and navigation communications
Connected toys and games
Rural internet access
Agricultural and farm networks
Utility smart meter and intelligent grid
Proximity sensors
Industrial automation controls
Smart home automation
EV car chargers
Appliances
Construction site connectivity
Smart signs and kiosks
Retail point-of-sale terminals
Vehicle-to-vehicle or Vehicle-to-Infrastructure communications
IP sensor networks
Biometric IDs and keypads
Warehouse Connectivity
Intelligent lighting controls
BT/ZigBee(™)/Z-Wave(™) to Wi-Fi HaLow gateways
Wi-Fi to Wi-Fi HaLow bridges
Wi-Fi HaLow client adapters/dongles
Smart city networks
2 Pin Descriptions
The MM6108-MF08651-US module has 38 pins, which are described in this section. The following illustration shows the top view of the module pins.
Figure 1: Pin diagram
1
GND
Power
Ground
2
GND
Power
Ground
3
GND
Power
Ground
4
JTAG_TCK
I
JTAG Clock
5
JTAG_TDI [1]
I
JTAG Data In
6
NC
NC
Do Not Connect
7
JTAG_TMS [1]
I
JTAG Mode Select
8
J TAG_TRST _N
I
JTAG Reset
9
JTAG_TDO [1]
O
JTAG Data Out
10
NC
I/O
Do Not Connect
11
GPIO_10 [2]
I/O
General Purpose IO10
12
GND
Power
Ground
13
GPIO_9 [2]
I/O
General Purpose IO9
14
GPIO_8 [2]
I/O
General Purpose IO8
15
GPIO_7 [2]
I/O
General Purpose IO7
16
SDIO_D1 [3]
I/O
SDIO D1
17
SDIO_D0 [3]
I/O
SDIO D0
18
SDIO_CLK
I/O
SDIO Clock
19
VDD_IO
Power
3.3V VDD_IO Supply
20
GND
Power
Ground
21
SDIO_CMD [3]
I/O
SDIO Command
SPI_MOSI
22
SDIO_D3 [3]
I/O
SDIO D3
SPI_CS
23
SDIO_D2 [3]
I/O
SDIO D2
24
GPIO_6 [2]
I/O
General Purpose IO6
25
VBAT
Power
3.3V VBAT Supply
26
GND
Power
Ground
27
GPIO_5 [2]
I/O
General Purpose IO5
28
GPIO_4 [2]
I/O
General Purpose IO4
29
GPIO_3 [2]
I/O
General Purpose IO3
30
GPIO_2 [2]
I/O
General Purpose IO2
31
GND
Power
Ground
32
VDD_FEM
Power
3.3V Frontend Module Supply
33
GPIO_1 [2]
I/O
General Purpose IO1
34
BUSY
O
Wi-Fi BUSY
35
RESET_N [4]
I
System Reset
36
WAKE [4]
I
Wake
37
GND
Power
Ground
38
ANT
Analog
Antenna
-
GND
Ground
Exposed ground - Connect to PCB GND
[1] JTAG pins should be tied to GND via a 10k pull down resistor
[2] All unused GPIO should be tied to GND via a 10k pull down resistor
[3] All SDIO bus pins except SDIO_CLK should be pulled up with a 10k-100k resistor as per the the SDIO standard
[4] Supplied from VBAT domain. Other digital pins are driven by the VDDIO domain.
3 Functional Description
The following sections describe the functions of the MM6108-MF08651-US module.
3.1 Block diagram
Figure 2: Functional Block Diagram
3.2 Power supply requirements
MM6108-MF08651-US module power is derived from a 3.0 to 3.6V supply on the VBAT pin and a 3.0 to 4.3V supply on the VDD_FEM pin. VBAT powers the module’s internal circuitry, while VDD_FEM powers the onboard ultra-long-range power amplifier. The module's transmitter power output can be increased by raising the supply voltage on the VDD_FEM pin to 4.3V, although this will increase overall power consumption.
VDDIO sets the IO voltage of the MM6108, which should be connected to the same power supply as the host MCU. The VDDIO voltage must be between 1.62V and 3.6V and must not exceed the voltage applied to VBAT.
3.3 SDIO host requirements
When selecting a CPU host to interface with the MM8108-MF08651 module via the SDIO interface, ensure the host supports SDIO 2.0 with SDIO clock speeds of up to 50 MHz. Slower clock speeds will impact the maximum achievable throughput.
The SDIO data and command lines should be pulled up with 10k-100k resistors per the SDIO 2.0 specification.
Most applications will benefit from the module's power-saving features. Two GPIOs, set as CMOS outputs, are required to drive the RESET and WAKE signals. A third GPIO, set as a CMOS input, is needed to receive the BUSY signal from the module.
In applications where the module must always be on, and the power-saving features can not be used, such as access points, the WAKE pin can be fixed to VBAT, reducing the need for GPIOs on the host processor to only one.
A schematic diagram detailing the recommended SDIO host interface circuit using the module’s power-saving features is shown below:
Figure 3: Recommended SDIO host interface circuit using power-saving features
A schematic diagram detailing the recommended SDIO host interface circuit for always-on applications is shown below:
Figure 4: Recommended SDIO host interface circuit for always-on applications
3.4 SPI host requirements
When selecting a CPU host to interface via SPI to the MM6108-MF08651-US module, consider the following recommendations to achieve the best throughput:
The host should support level-triggered interrupts.
The host should support full-duplex SPI mode.
The host should support DMA-backed transactions on the SPI bus.
Standard SPI can achieve up to 25 Mbps at 50 MHz, but this will be significantly reduced without DMA support. For example, an SPI interface with an 8-byte buffer per transaction might only achieve 2 Mbps throughput on the SPI bus.
Most applications will benefit from the module's power-saving features. Two GPIOs, set as CMOS outputs, are required to drive the RESET and WAKE signals. A third GPIO, set as a CMOS input, is needed to receive the BUSY signal from the module.
In applications where the module must always be on, and the power-saving features can not be used, such as access points, the WAKE pin can be fixed to VBAT, reducing the need for GPIOs on the host processor to only one.
A schematic diagram detailing the recommended SPI host interface circuit using the module’s power-saving features is shown below:
Figure 5: Recommended SPI host interface circuit using power-saving features
A schematic diagram detailing the recommended SPI host interface circuit for always-on applications is shown below:
Figure 6: Recommended SPI host interface circuit for always-on applications
3.5 Digital interfaces
All unused digital IO pins must be pulled up or down to prevent floating pins. Failure to do so will result in a higher leakage current on the VDDIO supply.
3.6 Sleep/Wake Sequencing
3.6.1 Host initiates wake sequence
Figure 7: Host-initiated wake sequence diagram
The driver raises the wake pin and waits for a static period of 10 ms before initializing the shared communication bus and initiating host interface activity. On MM6108, this period is typically 10 ms.
After completing communication, the driver will wait a static period, b, before lowering the wake pin (assuming no further communication has occurred). Depending on the nature of the communication (802.11 data vs. commands), this period can range from 5 to 90ms.
After the wake pin has fallen, the MM6108 will wait for a period, c, before initiating hardware sleep. This dynamic period will differ depending on the power-saving protocol and other chip-specific factors.
3.6.2 MM6108-MF08651 initiates wake sequence with host interface disabled
Figure 8: Module-initiated wake sequence with host interface disabled diagram
The MM6108 wakes from sleep and realizes it needs to pass traffic or an event to the host. It begins by asserting the busy pin.
The busy pin will fire an interrupt on the host, after which the host will immediately:
Raise the Wake PIN.
Wait a static period, 10ms
Initializes / enables the shared host interface.
After asserting the busy pin, the MM6108 will initiate host interface communication immediately. It does not wait until the host ‘enables’ the shared host interface. This is okay, as the bus transaction will be waiting for the host, and an interrupt should fire as soon as the host enables bus interrupts.
The busy pin will drop immediately once the MM6108 no longer needs to converse with the host. The host will wait a static period, b, before dropping the wake pin.
After the wake pin has fallen, the MM6108 will wait for a period, c, before initiating hardware sleep.
3.6.3 MM6108-MF08651 initiates communication with host interface enabled
Figure 9: Module-initiated wake sequence with host interface enabled diagram
The MM6108 was previously woken by the host for communication.
Sometime after wake and host->MM6108 communication, the MM6108 realizes it needs to send data back to the host (MM6108->host). It will assert the busy pin.
The busy pin will fire an interrupt on the host, after which it will immediately:
Process the interrupt but take no further action, as the wake pin has already been asserted and the shared host interface is currently enabled/initialized.
After MM6108->host communication completion, hardware sleep will be initiated as described above.
4 Electrical Characteristics
4.1 Absolute max ratings
Stress beyond absolute maximum ratings may cause permanent damage to the MM6108-MF08651-US module. Functional operation is only guaranteed for recommended operating conditions. Operation of the device outside the recommended conditions may result in a reduced lifetime and reliability problems, even if the absolute maximum ratings are not exceeded.
Table 1: Absolute max ratings
VBAT voltage
-0.3
4.3
V
VDD_FEM voltage
-0.3
4.3
V
Voltage on digital I/O pin
-0.3
4.3
V
Voltage on analog/RF pin
-0.3
1.2
V
Storage temperature
-40
125
°C
RF input power (CW)
-
6
dBm
4.2. Immunity
Table 2: Immunity
Electrostatic discharge (ESD) performance
Human body model (HBM), per ANSI / ESDA / JEDEC JS001
RF Input
-1000
1000
V
Electrostatic discharge (ESD) performance
Human body model (HBM), per ANSI / ESDA / JEDEC JS001
All pins except RF Input
-2000
2000
V
Electrostatic discharge (ESD) performance
Charged device model (CDM), per JESD22-C101
All pins
-500
500
V
4.3 Recommended operating conditions
Table 3: Recommended operating conditions
Ambient temperature
-40
2 5
85
°C
VBAT
3.0
3.3
3.6
V
VDD_FEM
3.0
3.3
4.3
V
VDDI O [1]
1.62
3.3
3.6
V
Digital I/O voltage
0
3.3
VDDIO
V
RESET / WAKE I/O Voltage
0
3.3
VBAT
V
[1] VDDIO should not exceed VBAT
Performance specifications are achieved under typical operating conditions unless otherwise specified.
4.4 Power consumption
4.4.1 Transmit power consumption
Table 4: Transmit power consumption
MCS 0
1 MHz channel
57
152
58
168
mA
MCS 0
2 MHz channel
60
152
61
168
mA
MCS 0
4 MHz channel
66
151
66
160
mA
MCS 0
8 MHz channel
78
147
77
154
mA
MCS 7
1 MHz channel
51
104
53
122
mA
MCS 7
2 MHz channel
55
104
57
123
mA
MCS 7
4 MHz channel
62
102
64
119
mA
MCS 7
8 MHz channel
72
99
76
117
mA
4.4.2 Receive power consumption
Table 5: Receive power consumption
Listen
1 MHz channel
25
26
35
4
4.5
4.7
mA
Listen
2 MHz channel
26
28
35
4
4.5
4.7
mA
Listen
4 MHz channel
30
32
40
4
4.5
4.7
mA
Listen
8 MHz channel
35
37
46
4
4.5
4.7
mA
Active receive MCS7
1 MHz channel
26
27
36
4
4.5
4.7
mA
Active receive MCS7
2 MHz channel
30
30
40
4
4.5
4.7
mA
Active receive MCS7
4 MHz channel
38
40
49
4
4.5
4.7
mA
Active receive MCS7
8 MHz channel
53
54
67
4
4.5
4.7
mA
Active receive MCS0
1 MHz channel
26
28
37
4
4.5
4.7
mA
Active receive MCS0
2 MHz channel
29
30
39
4
4.5
4.7
mA
Active receive MCS0
4 MHz channel
36
36
47
4
4.5
4.7
mA
Active receive MCS0
8 MHz channel
48
50
63
4
4.5
4.7
mA
4.4.3 Sleep power consumption
Table 6: Sleep power consumption
Snooze
RC Oscillator o n , Memory retained, wake on timer
9.5
42
370
0.001
0.05
0.55
uA
Deep sleep
RC Oscillator o n , wake on timer
0.8
1
1.8
0.001
0.05
0.55
uA
Hibernate
Power off, wait for external interrupt
0.03
0.05
1
0.001
0.05
0.55
uA
4.4.4 DTIM3 power consumption
Table 7: DTIM3 power consumption
S1G beacons
1 MHz channel
395
47
393
48
uA
S1G beacons
2 MHz channel
395
47
393
48
uA
S1G beacons
4 MHz channel
280
25
271
26
uA
S1G beacons
8 MHz channel
280
25
268
26
uA
S1G beacons with proprietary DTIM signaling 1
1 MHz channel
190
13
187
14
uA
S1G beacons with proprietary DTIM signaling 1
2 MHz channel
190
13
187
14
uA
S1G beacons with proprietary DTIM signaling 1
4 MHz channel
190
9
168
11
uA
S1G beacons with proprietary DTIM signaling 1
8 MHz channel
190
9
168
11
uA
4.4.5 DTIM10 power consumption
Table 8: DTIM10 power consumption
S1G beacons
1 MHz channel
155
15
145
16
uA
S1G beacons
2 MHz channel
155
15
144
16
uA
S1G beacons
4 MHz channel
115
8
109
9
uA
S1G beacons
8 MHz channel
115
8
109
9
uA
S1G beacons with proprietary DTIM signaling 1
1 MHz channel
95
5
88
6
uA
S1G beacons with proprietary DTIM signaling 1
2 MHz channel
95
5
88
6
uA
S1G beacons with proprietary DTIM signaling 1
4 MHz channel
90
5
80
5
uA
S1G beacons with proprietary DTIM signaling 1
8 MHz channel
90
5
80
5
uA
[1] Signaling that indicates whether a power-saving STA should receive and process an entire beacon
4.5 RF Specifications
4.5.1 Receiver Sensitivity
Sensitivities for 10% packet error rate, 1000 byte packets.
Table 9: Receiver sensitivity
10
BPSK
1/2 x 2
0.17
N/A
N/A
N/A
-107
N/A
N/A
N/A
0
BPSK
1/2
0.33
0.72
1.5
3.3
-105
-103
-101
-97
1
QPSK
1/2
0.67
1.4
3.0
6.5
-102
-100
-97
-93
2
QPSK
3/4
1.0
2.2
4.5
9.8
-99
-97
-95
-91
3
16-QAM
1/2
1.3
2.9
6.0
13
-96
-94
-91
-88
4
16-QAM
3/4
2.0
4.3
9.0
20
-93
-90
-88
-85
5
64-QAM
2/3
2.7
5.8
12
26
-89
-87
-84
-80
6
64-QAM
3/4
3.0
6.5
14
29
-88
-85
-83
-79
7
64-QAM
5/6
3.3
7.2
15
33
-87
-84
-81
-77
4.5.2 Transmitter Output Power
Note: The following transmit power levels are for IEEE compliance for 802.11ah. They do not consider any backoffs needed for regional spectrum compliance (eg, FCC, IC, TELEC).
Table 10: Transmitter output
1, 2 MHz
MCS 0
20
21
22
22
23.5
24.5
dBm
1, 2 MHz
MCS 7
16
17
18.5
18.5
20
21
dBm
4 Mhz
MCS 0
20.5
21
22
22
23.5
24.5
dBm
4 Mhz
MCS 7
16
17
18
18.5
20
20.5
dBm
8 Mhz
MCS 0
20.5
21
21.5
21.5
23
24.5
dBm
8 Mhz
MCS 7
15.5
17
17.5
18
19.5
20.5
dBm
4.6 Digital specifications
Figure 10: Powering on and reset timing diagram
Table 11: Digital specifications
V IL_nRST
Reset threshold
450
mV
t 0
Time between VBAT brought up (3.3V) and RESET_N being activated
50
μs
t 1
Duration of RESET_N signal level < VIL_nRST to reset the chip
1000
μs
t B
Boot Time
6
ms
Table 12: Digital Specifications
V IL_GPIO
Low input threshold for all GPIO and SDIO pins
1.8
-0.3
0.63
V
V IL_GPIO
Low input threshold for all GPIO and SDIO pins
2.5
-0.3
0.7
V
V IL_GPIO
Low input threshold for all GPIO and SDIO pins
3.3
-0.3
0.8
V
V IH_GPIO
High input threshold for all GPIO and SDIO pins
1.8
1.17
3.6
V
V IH_GPIO
High input threshold for all GPIO and SDIO pins
2.5
1.7
3.6
V
V IH_GPIO
High input threshold for all GPIO and SDIO pins
3.3
2.0
3.6
V
V OL_GPIO
Low output voltage for all GPIO and SDIO pins assuming a 8mA load
1.8
0.13
0.38
V
V OL_GPIO
Low output voltage for all GPIO and SDIO pins assuming a 8mA load
2.5
0.10
0.27
V
V OL_GPIO
Low output voltage for all GPIO and SDIO pins assuming a 8mA load
3.3
0.08
0.18
V
V OH_GPIO
High output voltage for all GPIO and SDIO pins assuming a 8mA load
1.8
1.34
1.70
V
V OH_GPIO
High output voltage for all GPIO and SDIO pins assuming a 8mA load
2.5
2.20
2.41
V
V OH_GPIO
High output voltage for all GPIO and SDIO pins assuming a 8mA load
3.3
3.07
3.23
V
V OL_SDIO
Low output voltage for all SDIO pins assuming a 8mA load
1.8
0.17
0.52
V
V OL_SDIO
Low output voltage for all SDIO pins assuming a 8mA load
2.5
0.14
0.36
V
V OL_SDIO
Low output voltage for all SDIO pins assuming a 8mA load
3.3
0.11
0.24
V
V OH_SDIO
High output voltage for all SDIO pins assuming a 8mA load
1.8
1.19
1.67
V
V OH_SDIO
High output voltage for all SDIO pins assuming a 8mA load
2.5
2.10
2.39
V
V OH_SDIO
High output voltage for all SDIO pins assuming a 8mA load
3.3
2.99
3.21
V
5 Physical Dimensions
Figure 11: Package dimensions
6 Recommended PCB Footprint
Figure 12: PCB Footprint diagram
7 Certification
7.1 FCC
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one of the following measures:
Reorient or relocate the receiving antenna
Increase the separation between the equipment and receiver
Connect the equipment into an outlet on a circuit different from that to which the receiver is connected
Consult the dealer or an experienced radio/TV technician for help
FCC caution: Any changes or modifications not expressly approved by the party responsible for compliance could void the user’s authority to operate this equipment.
This device complies with Part 15 of the FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.
7.1.1 FCC Radiation Exposure Statement:
This equipment complies with FCC radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance 20cm between the radiator and your body.
7.1.2 Important Note To Integrators
This module is intended for OEM integrators. It is only FCC authorized for the specific rule parts listed on the grant, and the host product manufacturer is responsible for compliance with any other FCC rules that apply to the host not covered by the modular transmitter grant of certification. The final host product still requires Part 15 Subpart B compliance testing with the modular transmitter installed.
Additional testing and certification may be necessary when multiple modules are used.
7.1.3 End Product User Manual Requirement
In the user manual of the end product, the end user has to be informed to keep at least 20cm of separation with the antenna while this end product is installed and operated. The end user has to be informed that the FCC radio-frequency exposure guidelines for an uncontrolled environment can be satisfied.
The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user’s authority to operate this equipment.
This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation.
7.1.4 End Product Label Requirement
The end product must be labeled in a visible area with the following:
Figure 13: End Product Label Requirement
Contains FCC ID: 2A74O-DB3F2B This device complies with Part 15 of FCC rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference and (2) this device must accept any interference received, including interference that may cause undesired operation.
7.2. IC
This device contains licence-exempt transmitter(s)/receiver(s) that comply with Innovation, Science and Economic Development Canada’s licence-exempt RSS(s). Operation is subject to the following two conditions:
(1) This device may not cause interference.
(2) This device must accept any interference, including interference that may cause undesired operation of the device.
Cet appareil contient des émetteurs / récepteurs exempts de licence qui sont conformes au (x)
RSS (s) exemptés de licence d’Innovation, Sciences et Développement économique Canada. L’opération est soumise aux deux conditions suivantes:
(1) Cet appareil ne doit pas provoquer d'interférences.
(2) Cet appareil doit accepter toute interférence, y compris les interférences susceptibles de provoquer un fonctionnement indésirable de l'appareil.
This radio transmitter 29791-628C73 has been approved by Innovation, Science and Economic Development Canada to operate with the antenna types listed below, with the maximum permissible gain indicated. Antenna types not included in this list that have a gain greater than the maximum gain indicated for any type listed are strictly prohibited for use with this device.
Le présent émetteur radio 29791-628C73 a été approuvé par Innovation, Sciences et Développement économique Canada pour fonctionner avec les types d'antenne énumérés ci-dessous et ayant un gain admissible maximal d'antenne. Les types d'antennes non inclus dans cette liste qui ont un gain supérieur au gain maximal indiqué pour tout type listé sont strictement interdits pour une utilisation avec cet appareil.
7.2.1 IC Radiation Exposure Statement:
This equipment complies with IC RSS-102 radiation exposure limits set forth for an uncontrolled environment. This equipment should be installed and operated with a minimum distance of 20cm between the radiator & your body.
Cet équipement est conforme aux limites d'exposition aux rayonnements IC établies pour un environnement non contrôlé. Cet équipement doit être installé et utilisé avec un minimum de 20 cm de distance entre la source de rayonnement et votre corps.
7.2.2 Important Note To Integrators
This module is intended for OEM integrators. The OEM integrator is responsible for complying with all the rules that apply to the product into which this certified RF module is integrated. Additional testing and certification may be necessary when multiple modules are used. Any changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment.
7.2.3 End Product User Manual Requirement
In the users manual of the end product, the end user has to be informed to keep at least 20 cm separation with the antenna while this end product is installed and operated. The end user has to be informed that the IC radio-frequency exposure guidelines for an uncontrolled environment can be satisfied.
The end user has to also be informed that any changes or modifications not expressly approved by the manufacturer could void the user's authority to operate this equipment. Operation is subject to the following two conditions:
(1) this device may not cause harmful interference
(2) this device must accept any interference received, including interference that may cause undesired operation.
7.2.4 End Product Label Requirement
The end product must be labeled in a visible area with the following:
Figure 14: End Product Label Requirement
Contains IC: 29791-628C73
The Host Model Number (HMN) must be indicated at any location on the exterior of the end product, product packaging, or product literature, which shall be available with the end product or online.
8 Part Numbers and Ordering Information
Table 13: Part number and ordering information
MM6108-MF08651-US
Tray
38
14.0 x 18.5 x 2.1
IEEE 802.11ah Sub-1 GHz 1/2/4/8 MHz Wi-Fi HaLow Module
9 Handling and Storage
The MM6108-MF08651-US module is a moisture-sensitive device rated at Moisture Sensitive Level 3 (MSL3) per IPC/JEDEC J-STD-20.
After opening the moisture-sealed storage bag, modules that will be subjected to reflow solder or other high-temperature processes must be:
Mounted to a circuit board within 168 hours at factory conditions (≤30°C and <60% RH)
OR
Continuously stored per IPC/JEDEC J-STD-033
Modules exposed to moisture and environmental conditions exceeding packaging and storage conditions MUST be baked before mounting according to IPC/JEDEC J-STD-033.
Failure to meet packaging and storage conditions will result in irreparable damage to modules during solder reflow.
10 Revision History
DS102
17 Jun 2025
Updated formatting
DS101
28 Feb 2025
General updates to layout and formatting Higher voltage VFEM impacts added
DS100
16 Dec 2023
Initial release
Morse Micro provides this information "as is" without warranties of any kind, express or implied. No guarantee is made as to the accuracy, completeness, or suitability of this information or Morse Micro’s products for any specific purpose. Use of this information and products is at the user’s sole risk. Morse Micro products are not designed or tested for use in mission-critical systems, and should not be used in such applications. Performance specifications are based on internal testing and are believed to be reliable; however, they are not guaranteed. It is the Buyer’s responsibility to test and validate all product performance, compatibility, and compliance, both in isolation and within end applications. Morse Micro assumes no liability for the use or application of any product, circuit, or information described herein. No license or other rights, express or implied, are granted under Morse Micro’s intellectual property. This document contains proprietary information of Morse Micro and is subject to change without notice.
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