> For the complete documentation index, see [llms.txt](https://docs.morsemicro.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.morsemicro.com/datasheets/mm8108-datasheet.md). # MM8108 Datasheet v4 ## 1 Product Overview ### 1.1 Introduction Wi-Fi HaLow (pronounced "HEY-low") is the first global Wi-Fi standard (IEEE 802.11ah) specifically designed to meet the needs of the Internet of Things (IoT). It’s an open standard wireless network technology operating in the sub-1 GHz license-exempt RF bands (850 MHz to 950 MHz range), so it doesn’t incur ongoing monthly costs like cellular/mobile network connections. By operating in the sub-1 GHz range, this low-power wireless protocol can connect more IoT devices over much longer distances and with significantly lower power consumption than traditional Wi-Fi. Morse Micro, the world’s leading Wi-Fi HaLow solutions provider, offers several Wi-Fi HaLow connectivity solutions. The MM8108 SoC is a single-chip solution that incorporates radio, PHY, and MAC functions, all of which are compliant with the IEEE 802.11ah standard. It supports world-leading power efficiency and PHY rates up to 43.3 Mbps using world-first 256-QAM modulation at an 8 MHz bandwidth. It is ideal for power-sensitive and high-speed applications. Its integrated power amplifier (PA) offers world-leading transmit performance and energy efficiency with on-chip amplification of up to 26 dBm, which is ideal for low-cost devices. For ultra-long reach applications, the MM8108 can be paired with an external PCB mount power amplifier, typically included in front-end modules (FEMs). The high-performance integrated low-noise amplifier (LNA) offers exceptional receive sensitivity. These features, combined with digital transmit filtering and pre-distortion circuits, result in an advanced transceiver design that ensures out-of-the-box compatibility with all global Wi-Fi HaLow regulatory environments while reducing external component costs by eliminating the requirement for expensive external filters. MM8108 supports a USB 2.0 High-Speed host interface and an SDIO/SPI host interface, offering solution architects flexibility when integrating Wi-Fi HaLow connectivity into their existing solution. With a footprint of only 5 mm x 5 mm and a higher level of integration than previous generations of chipsets, the MM8108 can fit even smaller designs while substantially reducing the overall cost of materials. MM8108 supports WPA3 and all standard security features required for Wi-Fi HaLow product certifications. ### 1.2 Features * Single-stream maximum PHY rate of 43.3 Mbps at 8 MHz bandwidth * Radio supporting all global Sub-1 GHz frequency bands * Frequency Range: 850 MHz to 950 MHz * Channel width options of 1/2/4/8 MHz * High power and extremely high efficiency integrated PA with maximum 26 dBm (400 mW) output power at 45% PA efficiency and 37% SoC efficiency * Novel PA architecture maintains efficiency at power backoff * Low-power receiver with integrated LNA, NF < 4 dB * Compatible with external LNA, PA for higher power or sensitivity requirements * 802.11ah OFDM PHY with Wi-Fi Alliance Wi-Fi HaLow certification * BPSK, QPSK, 16-QAM, 64-QAM and 256-QAM * Automatic frequency and gain control * Packet detection and channel equalization * Forward Error Correction (FEC) coding and decoding * Modulation and Coding Scheme (MCS) levels 0-10 * 1 MHz duplicate mode * Optional traveling pilots * 802.11ah MAC with Wi-Fi Alliance Wi-Fi HaLow certification * Support for Station (STA) and Access Point (AP) roles * Listen-Before-Talk (LBT) access with energy detection * 802.11 power save * 802.11 fragmentation and defragmentation * Power-Saving Target Wake Time (TWT) support for extended battery life * Automatic and manual MCS rate selection * On-chip software stack assisting with host offload of Wi-Fi connection management * USB 2.0 High-Speed compliant device interface * Integrated USB 2.0 PHY and device interface supporting High-Speed mode at 480 Mbps * SDIO 2.0 compliant device interface * SDIO 2.0 High-Speed at 50 MHz max for 200 Mbps * Support for 1-bit and 4-bit data mode * Support for SPI mode operation at up to 80 MHz for 80 Mbps * Power Management Unit (PMU) supporting various modes of operation * Single supply 3.0-3.6 V for integrated DC-DCs and LDOs * Multiple low-power modes (hibernate, deep sleep, snooze, USB snooze) support extreme power environments * Support for an external real-time clock source providing the highest accuracy timing for sleep modes * Wide spectrum of security features * Wi-Fi layer security, including Wi-Fi Protected Access version 3 (WPA3), Protected Management Frames (PMF), and Opportunistic Wireless Encryption (OWE) * Hardware support for Advanced Encryption Standard (AES) and Secure Hash Algorithm version 2 (SHA-2) functions (SHA-256, SHA-384, SHA-512) ### 1.3 Applications For Internet of Things (IoT) and Machine-to-Machine (M2M) applications, such as: * Surveillance Cameras and Sensors * Cloud Connectivity * Low-power Sensor Networks * Building Automation Systems * Asset Tracking and Management * Machine Performance Monitors and Sensors * Building Access Control and Security * Drone Video and Navigation Communications * Connected Toys and Games * Rural Internet Access * Agricultural Networks * Utility Smart Meter and Intelligent Grid * Proximity Sensors * Industrial Automation Controls * Smart Home Automation * EV Car Chargers * Appliances * Construction Site Connectivity * Smart Signs and Kiosks * Retail Point-of-Sale Terminals * Vehicle-to-Vehicle Communications * IP Sensor Networks * Biometric IDs and Keypads * Warehouse Connectivity * Intelligent Lighting Controls * BT/ZigBee™/Z-Wave™ to Wi-Fi HaLow Gateways * Smart City Networks ## 2 Pin Overview ### 2.1 Pin Layout The MM8108 device package features 79 pins in a 5 mm x 5 mm package, as described in this section. ![Figure 1: Pin diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/HECTsBtrc9PWYl1wma6k/Unknown%20image) ### 2.2 Pin Descriptions The two buck converters on MM8108 are referred to as BUCK and BUCK\_TX, which have output voltages of 1.2 V and 1.8 V, respectively. **Table 1: Pin description** | Pin | Default Functionality Pin Name | Default Functionality Type | Default Functionality Description | Alternative 1 Pin Name | Alternative 2 Pin Name | | --- | ------------------------------ | -------------------------- | ---------------------------------------- | ---------------------- | ---------------------- | | A1 | GND | Ground | | | | | A2 | XON | Analog | 32 MHz crystal connection | | | | A3 | XOP | Analog | 32 MHz crystal connection | | | | A4 | GND | Ground | | | | | A5 | VBUCK | Supply | BUCK voltage | | | | A6 | WAKE\_UP | Analog | External wake from Deep Sleep and Snooze | | | | A7 | VBUCK\_FB | Supply | Voltage sense pin for BUCK output | | | | A8 | VBAT\_PWR | Supply | 3.3 V VBAT supply for BUCK | | | | A9 | GND | Ground | | | | | B1 | RTC\_XON | Analog | RTC XTAL connection, NC if unused | | | | B2 | NC | Not connected | | | | | B3 | NC | Not connected | | | | | B4 | VBUCK | Supply | BUCK output voltage | | | | B5 | VBAT\_AON | Supply | 3.3 V VBAT supply for the AON unit | | | | B6 | RESET\_N | Analog | Asynchronous chip reset (active low) | | | | B7 | GND | Ground | | | | | B8 | GND | Ground | | | | | B9 | VSW | Supply | BUCK switching node | | | | C1 | RTC\_XOP | Analog | RTC XTAL connection, NC if unused | | | | C2 | NC | Not connected | | | | | C3 | NC | Not connected | | | | | C4 | NC | Not connected | | | | | C5 | GND | Ground | | | | | C6 | GPAIO | Analog | Analog test signal (keep grounded) | | | | C7 | NC | Not connected | | | | | C8 | GND | Ground | | | | | C9 | GND | Ground | | | | | D1 | GND | Ground | | | | | D2 | GND | Ground | | | | | D3 | LO\_TEST | Analog | Analog test signal (keep grounded) | | | | D4 | GND | Ground | | | | | D5 | GPIO \_12 | Digital I/O | | FEM\_Control | FEM\_Control | | D6 | JTAG\_TMS | Digital I/O | JTAG mode select | | | | D7 | JTAG\_TDO | Digital I/O | JTAG data out | | | | D8 | SDIO\_D3 | Digital I/O | SDIO/SPI data line | SPI\_CS | QSPI\_D3 | | D9 | SDIO\_D0 | Digital I/O | SDIO/SPI data line | SPI\_MISO | QSPI\_D0 | | E1 | RFIN | RF | Receiver input | | | | E2 | GND | Ground | | | | | E3 | NC | Not connected | | QSPI\_CSB\_1 | QSPI\_CSB\_1 | | E4 | GPIO \_9 | Digital I/O | | | | | E5 | GPIO \_11 | Digital I/O | | FEM\_Control | FEM\_Control | | E6 | JTAG\_TCK | Digital I/O | JTAG clock | | | | E7 | JTAG\_TDI | Digital I/O | JTAG data in | | | | E8 | SDIO\_D2 | Digital I/O | SDIO/SPI data line | 47 kΩ pull-up needed | QSPI\_D2 | | E9 | SDIO\_D1 | Digital I/O | SDIO/SPI data line | SPI\_IRQ | QSPI\_D1 | | F1 | GND | Ground | | | | | F2 | Depopulated | | | | | | F3 | GND | Ground | | | | | F4 | GPIO \_8 | Digital I/O | | BUSY | BUSY | | F5 | GPIO \_10 | Digital I/O | | FEM\_Control | FEM\_Control | | F6 | GND | Ground | | | | | F7 | GND | Ground | | | | | F8 | SDIO\_CMD | Digital I/O | SDIO/SPI command/data line | SPI\_MOSI | QSPI\_CSB | | F9 | SDIO\_CLK | Digital I/O | SDIO/SPI clock input | SPI\_SCK | QSPI\_CLK | | G1 | RF\_OUT | RF | Transmitter output | | | | G2 | Depopulated | | | | | | G3 | VBUCK\_TX | Supply | BUCK\_TX voltage for the transmitter | | | | G4 | GPIO \_7 | Digital I/O | | DBG\_UART\_MM\_RX | DBG\_UART\_MM\_RX | | G5 | GPIO \_3 | Digital I/O | | QSPI\_D1 | UART\_RX | | G6 | GPIO \_4 | Digital I/O | | QSPI\_D2 | UART\_RTS | | G7 | GPIO \_5 | Digital I/O | | QSPI\_D3 | UART\_CTS | | G8 | VDDIO | Power | Host supply for digital I/O | | | | G9 | GND | Ground | | | | | H1 | GND | Ground | | | | | H2 | VBUCK\_TX | Supply | BUCK\_TX voltage for the transmitter | | | | H3 | GPIO \_6 | Digital I/O | | DBG\_UART\_MM\_TX | DBG\_UART\_MM\_TX | | H4 | GPIO \_0 | Digital I/O | | QSPI\_CLK | | | H5 | GPIO \_1 | Digital I/O | | QSPI\_CSB\_0 | | | H6 | BUSY | Digital I/O | BUSY signal output | QSPI\_D0 | UART\_TX | | H7 | GND | Ground | | | | | H8 | GND | Ground | | | | | H9 | VSW\_TX | Supply | BUCK\_TX switching node | | | | J1 | GND | Ground | | | | | J2 | VBUCK\_TX | Supply | BUCK\_TX voltage for the transmitter | | | | J3 | GND | Ground | | | | | J4 | USB\_DP | USB I/O | USB Data Plus (DP) line | | | | J5 | USB\_DM | USB I/O | USB Data Minus (DM) line | | | | J6 | USB\_VCC33A | Supply | USB 3.3 V supply | | | | J7 | VBUCK\_FB\_TX | Supply | Voltage sense pin for BUCK\_TX | | | | J8 | VBAT\_PWR\_TX | Supply | 3.3V VBAT supply to BUCK\_TX | | | | J9 | GND | Ground | | | | **Table 2: Alternative pin functionality description** | Alternative Pin Functionality Descriptions Pin Name | Alternative Pin Functionality Descriptions Description | | --------------------------------------------------- | ------------------------------------------------------ | | FEM\_Control | External front-end module control | | SPI\_SCK | SPI host interface serial clock | | SPI\_MOSI | SPI host interface master out, slave in | | SPI\_MISO | SPI host interface master in, slave out | | SPI\_IRQ | SPI host interface interrupt line | | SPI\_CS | SPI host interface chip select | | QSPI\_CLK | QSPI interface clock | | QSPI\_D0 | QSPI interface data line 0 | | QSPI\_D1 | QSPI interface data line 1 | | QSPI\_D2 | QSPI interface data line 2 | | QSPI\_D3 | QSPI interface data line 3 | | QSPI\_CSB\_0 | QSPI interface chip select device 0 | | QSPI\_CSB\_1 | QSPI interface chip select device 1 | | BUSY | Busy signal output | | DBG\_UART\_MM\_RX | Debug UART receive data | | DBG\_UART\_MM\_TX | Debug UART transmit data | | UART\_RX | UART host interface receive data | | UART\_TX | UART host interface transmit data | | UART\_RTS | UART host interface request to send | | UART\_CTS | UART host interface clear to send | ## 3 Functional Description The following sections describe the functions of the MM8108 device. ### 3.1 Functional Block Diagram ![Figure 2: Functional block diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/RDckk9oYQa3eLNDzhspG/Unknown%20image) ### 3.2 Clocks #### 3.2.1 XTAL Clock Deriving clocks in the RF and digital subsystems requires a 32 MHz crystal (XTAL) component. As shown in Figure 3, a Pierce oscillator circuit is used. ![Figure 3: Crystal circuit](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/viaaQh1YiNCXm0nZcauu/Unknown%20image) The crystal is connected between pins XOP & XON. The crystal load capacitance and driver is provided internally inside the chip (denoted in the gray box above). No external load capacitors are required on the PCB. The crystal component should meet the following specifications across the expected temperature range of operation to comply with 802.11ah standards for frequency offset and achieve the specified sensitivity. **Table 3: Crystal component specification** | XTAL Specifications | Min | Typ | Max | Units | | ------------------- | --- | --- | --- | ----- | | Frequency tolerance | - | - | 20 | ppm | | ESR | 10 | - | 100 | Ω | | Load capacitance | - | 8 | - | pF | Note: The crystal component frequency tolerance above is without trimming and is across temperature for the component's lifetime. The equipment designer is responsible for selecting a crystal component that complies with these specifications. #### 3.2.2 RTC XTAL Clock A 32.768 kHz crystal driver circuit is available for optional use as a real-time clock (RTC) source. This source provides the highest accuracy timing for system sleep modes compared with the on-chip RC oscillator, which is used if an RTC XTAL is absent. ![Figure 4: RTC crystal circuit](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/T7NyZ6xRwF7feo8L7y8N/Unknown%20image) As shown in Figure 4, the crystal should be connected between pins RTC\_XOP and RTC\_XON. Load capacitors CL must be placed at these pins and coupled to Ground. The capacitance values should follow the suggestions of the crystal datasheet. The crystal stability should be +/-30 ppm or better for accurate sleep time control. **Table 4: RTC crystal component specification** | RTC XTAL Specifications | Min | Typ | Max | Units | | ----------------------- | --- | ---- | --- | ----- | | Frequency tolerance | – | - | 30 | ppm | | ESR | - | 90 | - | kΩ | | Load capacitance | - | 12.5 | - | pF | ### 3.3 Power Management #### 3.3.1 Power Supply All power is derived from a 3.0 V to 3.6 V power source connected to VBAT\_PWR (A8), VBAT\_AON (B5), and VBAT\_PWR\_TX (J8). VDDIO (G8) can be connected to the same 3.0 V to 3.6 V power source or, if available, to the host's dedicated VDDIO rail. For optimal performance, 4.7 uF, 470 nF, 10 uF, and 470 nF decoupling capacitors are required at VBAT (A8), VBAT\_AON (B5), VBAT\_PWR\_TX (J8), and VDDIO (G8), respectively. VSW (B9) requires a 2.2 uH/10 uF LC filter and a 4.7 uF decoupling capacitor at VBUCK (A5, B4). The VBUCK\_FB (A7) feedback connection must be as close as possible to the load pin VBUCK (A5, B4). VSW\_TX (H9) requires a 1.5 uH/22 uF LC filter at VBUCK\_TX (G3, H2, J2). The VBUCK\_TX\_FB (J7) feedback connection must be as close as possible to the load pin VBUCK\_TX (G3, H2, J2). All ground pins should be connected to a solid ground plane on the second layer of the PCB. #### 3.3.2 Power Modes An internal Power Management Unit (PMU) provides multiple low-power modes that the chip may enter via firmware routines. **Table 5: Power modes overview** | Power Mode | Wake From RESET\_N (B6) | Wake From WAKE\_UP (A6) | Wake From Internal Timer | Wake From USB Signalling | 1 MB SRAM Retained | | ---------- | ----------------------- | ----------------------- | ------------------------ | ------------------------ | ------------------ | | Hibernate | Yes | No | No | No | No | | Deep Sleep | Yes | Yes | Yes | No | No | | Snooze | Yes | Yes | Yes | No | Yes | | USB snooze | Yes | Yes | Yes | Yes | Yes | Note: * Using RESET\_N (B6) to wake the chip will cause a complete chip reboot with no retention of any kind of memory **3.3.2.1 Hibernate** Hibernate mode draws the least current of the low-power modes. It may be exited only by toggling the RESET\_N (B6) pin, which causes the chip to reboot. While in hibernate mode, the chip will not respond to the WAKE\_UP (A6) pin or run an internal timer, and no internal memory will be retained. **3.3.2.2 Deep Sleep** Deep Sleep mode can be exited by toggling the RESET\_N (B6) pin, which causes a complete chip reboot, asserting the WAKE\_UP (A6) pin, or by using an internal timer (running on the real-time clock source). While in Deep Sleep mode, no internal memory will be retained. **3.3.2.3 Snooze** Snooze mode can be exited by toggling the RESET\_N (B6) pin, which causes a complete chip reboot, by asserting the WAKE\_UP (A6) pin, or by using an internal timer (running on the real-time clock source). If the chip resumes operation via the WAKE\_UP (A6) pin or an internal timer, 1 MB of SRAM memory will be retained. No internal memory will be retained if the chip is rebooted using the RESET\_N (B6) pin. **3.3.2.4 USB Snooze** USB snooze mode can be exited by toggling the RESET\_N (B6) pin, which causes a complete chip reboot by asserting the WAKE\_UP (A6) pin, using an internal timer (running on the real-time clock source), or by resuming signaling over the USB bus from the USB host. If the chip resumes operation via the WAKE\_UP (A6) pin, an internal timer, or USB resume signaling, 1 MB of SRAM memory will be retained. No internal memory will be retained if the chip is rebooted using the RESET\_N (B6) pin. ### 3.4 Boot/Reset Sequencing #### 3.4.1 Boot Timing ![Figure 5: Boot timing diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/fQmuIc4eVxduK0W3a3Yu/Unknown%20image) **Table 6: Boot timing overview** | Parameters | Description | Min | Max | Unit | | ---------- | ----------------------------------------------------------------- | --- | --- | ---- | | V IL\_nRST | Reset threshold | 450 | - | mV | | t 0 | Time between VBAT brought up (3.3 V) and RESET\_N being activated | 50 | - | μs | | t B | Boot time | - | 10 | ms | #### 3.4.2 Reset Timing ![Figure 6: Reset timing diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/joVWgDW5JnYoa6SJoT4c/Unknown%20image) **Table 7: Reset timing overview** | Parameters | Description | Min | Max | Unit | | ---------- | ---------------------------------------------------------------- | --- | --- | ---- | | V IL\_nRST | Reset threshold | 450 | - | mV | | t 1 | Duration of RESET\_N signal level < V IL\_nRST to reset the chip | 1 | - | ms | | t B | Boot time | - | 10 | ms | #### 3.4.3 Low-Power Modes Exiting any low-power mode takes at most 10 ms. ### 3.5 USB Host Interface A USB 2.0 High-Speed host interface is available, supporting device mode only at up to 480 Mbps. #### 3.5.1 Pin Description **Table 8: USB bus pins** | Pin | Pin Name | Description | | --- | ----------- | --------------------------------------- | | J4 | USB\_DP | High-speed differential pin, DP | | J5 | USB\_DM | High-speed differential pin, DM | | J6 | USB\_VCC33A | 3.3 V analog supply voltage for USB 2.0 | #### 3.5.2 Features * An integrated USB 2.0 PHY and MAC capable of up to High-Speed mode at 480 Mbps * Device endpoints implementing bulk data, isochronous transfers, and interrupts for the USB host driver to operate the chip as a network AP or STA * Suspend and resume power management functions * USB snooze mode with in-band wake * The USB link must be suspended to enter USB snooze mode. * The chip will initiate wake from USB snooze mode and return to normal operation mode when the USB host issues resume signaling over the USB bus (in-band). **Table 9: USB bus electrical specifications** | Parameter | Min | Typ | Max | Unit | | ------------------------------------------------------------ | --- | --- | --- | ---- | | USB\_VCC33A | 3.0 | 3.3 | 3.6 | V | | V noise\_33A (Allowable power noise on supply, 1 Hz-100 kHz) | - | - | 150 | mV | | I VCC33A | - | 8.1 | 8.4 | mA | ### 3.6 SDIO Host Interface A host interface is available via SDIO 2.0, capable of High-Speed mode and operating at 3.3 V. #### 3.6.1 Pins **Table 10: SDIO pins** | Pin | Pin Name | SDIO 4-bit Mode | SDIO 1-bit Mode | | --- | --------- | ----------------- | ----------------- | | F9 | SDIO\_CLK | Clock pin (input) | Clock pin (input) | | F8 | SDIO\_CMD | Command pin | Command pin | | D9 | SDIO\_D0 | Data pin 0 | Data pin 0 | | E9 | SDIO\_D1 | Data pin 1 | IRQ | | E8 | SDIO\_D2 | Data pin 2 | Unused | | D8 | SDIO\_D3 | Data pin 3 | Unused | #### 3.6.2 Bus Timing The SDIO clock rate supports up to 50 MHz. The SDIO bus always operates in High-Speed (25 Mbps) mode. ![Figure 7: SDIO device bus input timing diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/O92Od4TZsS4VRbGELoH2/Unknown%20image) ![Figure 8: SDIO device bus output timing diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/SBQUgM80hPf0gvOGNVMN/Unknown%20image) **Table 11: SDIO bus timing** | Parameter | Min | Max | Units | | -------------------------------------- | --- | --- | ----- | | Clock frequency | 0 | 50 | MHz | | Clock low time (t WL ) | 7 | - | ns | | Clock high time(t WH ) | 7 | - | ns | | Clock rise time (t LH ) | - | 3 | ns | | Clock fall time (t HL ) | - | 3 | ns | | Input setup time (t ISU ) | 6 | - | ns | | Input hold time (t IH ) | 2 | - | ns | | Output delay (t ODLY(max) ) | - | 14 | ns | | Output hold time (t ODLY(min) ) | 2.5 | - | ns | | Total system capacitance for each line | - | 40 | pF | ### 3.7 SPI Host Interface The SPI interface uses the pin layout as defined below, over which the modified SDIO protocol is used for communication. #### 3.7.1 Pins **Table 12: SPI bus pins** | Pin | Pin Name | SPI mode function | | --- | -------- | -------------------------------------------- | | D8 | CS | Chip select (active low) | | E9 | INT | Interrupt pin | | D9 | MISO | Master data in/slave data out | | F8 | MOSI | Master data out/slave data in | | F9 | CLK | Clock pin (input) | | E8 | Unused | Unused, needs to be pulled high for SPI mode | #### 3.7.2 Initialization in SPI Mode After power-on, the host interface can be brought up as either SDIO or SPI. Per the SDIO specification, the host must send a CMD0 while holding CS low (its asserted state) to switch the interface to SPI mode. For further details on the protocol, refer to the SD Specification Part E1 “SDIO Simplified Specification” version 2.00. #### 3.7.3 SPI Bus Timing The SPI clock rate supports up to 80 MHz. The SPI bus timing is identical to the SDIO bus timing, including considering MOSI and MISO as input and output timing, respectively. The SPI bus defaults to clock idling at logical 0 (CPOL=0), and data is launched and captured on the positive edges of the clock, as per SDIO High-Speed mode. After being initialized, the SPI bus may be configured to behave like CPHA=0 (drive output on negative edge, sample on positive edge). ### 3.8 GPIO #### 3.8.1 Features Up to 12 programmable General Purpose Input/Output (GPIO) pins are available. Each pin can be configured with a unique drive value and with driving enabled or disabled. The value of each pin can be read whether driving or not. Each pin can be configured to generate an interrupt based on level or edge (rising or falling). Inputs are synchronized to the main digital clock, so any pulses must be at least 31.25 us in length. There are internal pull-up and pull-down facilities in the pads and drive-strength selection. #### 3.8.2 Reset State GPIO pins will be undriven at boot and in a high impedance state. #### 3.8.3 Power-Save State The digital GPIOs can be programmed to retain their output state during power-saving modes. Digital GPIOs cannot be used to wake the chip. Only the dedicated WAKE\_UP (A6) pin can be used to wake the chip. If the RESET\_N (B6) pin is asserted while the chip is in any power-save mode, the chip will reboot, the retained digital GPIO state will be lost, and the pads will reset to high impedance. ## 4 Electrical Characteristics ### 4.1 Absolute Maximum Ratings Stress beyond absolute maximum ratings may cause permanent damage to the device. Operation is only guaranteed for recommended operating conditions. Operation of the device outside of recommended conditions may result in reduced lifetime and reliability problems, even if the absolute maximum ratings are not exceeded. **Table 13: Absolute maximum and minimum voltage ratings** | Parameter | Min | Max | Unit | | ----------------- | ---- | --- | ---- | | VBAT \_PWR | -0.3 | 3.6 | V | | VBAT\_PWR\_TX | -0.3 | 3.6 | V | | VBAT\_AON | -0.3 | 3.6 | V | | VDDIO | -0.3 | 3.6 | V | | RESET\_N/WAKE\_UP | -0.3 | 3.6 | V | | RF\_IN | -0.3 | 1.0 | V | ### 4.2 ESD Immunity **Table 14: ESD immunity specifications** | Parameter | Parameter | Parameter | Min | Max | Unit | | ----------------------------------------- | ----------------------------------------------------- | ------------------------ | ------ | ----- | ---- | | Electrostatic discharge (ESD) performance | Human body model (HBM), per ANSI / ESDA / JEDEC JS001 | RF Input | -1,000 | 1,000 | V | | Electrostatic discharge (ESD) performance | Human body model (HBM), per ANSI / ESDA / JEDEC JS001 | All pins except RF Input | -2,000 | 2,000 | V | | Electrostatic discharge (ESD) performance | Charged device model (CDM), per JESD22-C101 | All pins | -500 | 500 | V | ### 4.3 Recommended Operating Conditions **Table 15: Recommended operating conditions** | Parameter | Min | Typ | Max | Unit | | ------------------- | ---- | --- | --- | ---- | | Ambient temperature | -40 | - | 85 | °C | | Storage temperature | -40 | - | 125 | °C | | VBAT \_PWR | 3.0 | 3.3 | 3.6 | V | | VBAT\_PWR\_TX | 3.0 | 3.3 | 3.6 | V | | VBAT\_AON | 3.0 | 3.3 | 3.6 | V | | VDDIO | 2.25 | 3.3 | 3.6 | V | ### 4.4 Power Consumption #### 4.4.1 Active Transmit Current Consumption **Table 16: Transmit current consumption for VBAT, VBAT\_TX separated** | MCS Index | Current consumption (mA) per BW at V BAT 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 1 MHz | Current consumption (mA) per BW at V BAT 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 2 MHz | Current consumption (mA) per BW at V BAT 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 4 MHz | Current consumption (mA) per BW at V BAT 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 8 MHz | Current consumption (mA) per BW at V BAT\_TX 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 1 MHz | Current consumption (mA) per BW at V BAT\_TX 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 2 MHz | Current consumption (mA) per BW at V BAT\_TX 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 4 MHz | Current consumption (mA) per BW at V BAT\_TX 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V 8 MHz | | --------- | -------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------- | -------------------------------------------------------------------------------------------------- | ------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------ | | 10 | 51 | N/A | N/A | N/A | 281 | N/A | N/A | N/A | | 0 | 52 | 51 | 50 | 59 | 279 | 243 | 160 | 132 | | 1 | 52 | 51 | 50 | 59 | 278 | 243 | 159 | 131 | | 2 | 51 | 51 | 50 | 59 | 277 | 243 | 158 | 130 | | 3 | 51 | 51 | 50 | 59 | 266 | 242 | 158 | 130 | | 4 | 49 | 50 | 50 | 59 | 221 | 221 | 152 | 130 | | 5 | 44 | 47 | 48 | 58 | 144 | 174 | 128 | 125 | | 6 | 42 | 44 | 46 | 57 | 118 | 119 | 109 | 106 | | 7 | 36 | 39 | 44 | 54 | 88 | 96 | 98 | 95 | | 8 | 34 | 38 | 43 | 52 | 69 | 78 | 83 | 81 | | 9 | 32 | N/A | 40 | 49 | 54 | N/A | 63 | 58 | #### 4.4.2 Active Receive Current Consumption **Table 17: Active receive current consumption** | MCS Index | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V, R X signal at -70dBm 1 MHz | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V, R X signal at -70dBm 2 MHz | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V, R X signal at -70dBm 4 MHz | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW 100% duty cycle, T A =25 o C, V BAT = V DDIO =3.3 V, R X signal at -70dBm 8 MHz | | --------- | ------------------------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------------------------ | | 0 | 18 | 19 | 23 | 31 | | Max | 18 (MCS9) | 20 (MCS8) | 25 (MCS9) | 34 (MCS9) | #### 4.4.3 Listen Receive Current Consumption **Table 18: Listen receive current consumption** | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW T A =25 o C, V BAT = V DDIO =3.3 V, Rx signal at -70dBm 1 MHz | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW T A =25 o C, V BAT = V DDIO =3.3 V, Rx signal at -70dBm 2 MHz | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW T A =25 o C, V BAT = V DDIO =3.3 V, Rx signal at -70dBm 4 MHz | V BAT + V BAT\_TX + V DDIO Current consumption (mA) per BW T A =25 o C, V BAT = V DDIO =3.3 V, Rx signal at -70dBm 8 MHz | | ------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------ | ------------------------------------------------------------------------------------------------------------------------ | | 17 | 18 | 21 | 29 | #### 4.4.4 Low Power Current Consumption **Table 19: Low power current consumption** | Power Mode | Current Consumption T A =25 o C, V BAT = V DDIO =3.3 V V BAT + V BAT\_TX | Current Consumption T A =25 o C, V BAT = V DDIO =3.3 V V DDIO | Current Consumption T A =25 o C, V BAT = V DDIO =3.3 V Unit | | ---------- | ------------------------------------------------------------------------ | ------------------------------------------------------------- | ----------------------------------------------------------- | | Hibernate | <1 | <1 | μA | | Deep Sleep | <2 | <1 | μA | | Snooze | <20 | <1 | μA | | USB snooze | <500 | <1 | μA | #### 4.4.5 Standby Current Consumption (using SDIO/SPI Host Interface) **Table 20: Standby current consumption** | Mode | Condition: T A =25 o C, V BAT = V DDIO =3.3 V | V BAT + V BAT\_TX | V DDIO | Unit | | ------ | --------------------------------------------- | ----------------- | ------ | ---- | | DTIM3 | 2 MHz channel, RTC=RTC\_XTAL, beacon=long | 176 | <1 | μA | | DTIM10 | 2 MHz channel, RTC=RTC\_XTAL, beacon=long | 68 | <1 | μA | | DTIM40 | 2 MHz channel, RTC=RTC\_XTAL, beacon=long | 33 | <1 | μA | | DTIM3 | 2 MHz channel, RTC=RTC\_XTAL, beacon=short | 126 | <1 | μA | | DTIM10 | 2 MHz channel, RTC=RTC\_XTAL, beacon=short | 52 | <1 | μA | | DTIM40 | 2 MHz channel, RTC=RTC\_XTAL, beacon=short | 29 | <1 | μA | The DTIM (Delivery Traffic Indication Message) number (DTIMx) indicates how often a Wi-Fi HaLow station in power-saving Snooze mode wakes to receive traffic from the access point. It is expressed as a multiple of beacon intervals (multiples of 102.4 ms). For example, DTIM1 indicates that the station will wake up every 102.4 ms, while DTIM40 configures the station to wake up every 4.1 seconds. Configuring DTIM is a complex compromise between power consumption and latency. Increasing the DTIM will reduce the average power consumption, as the station spends a greater proportion of time in Snooze mode, which consumes significantly less power than in Listen mode. However, since the station is unable to receive traffic in Snooze mode, increasing DTIM also increases latency. DTIM settings should be optimized appropriately according to the use case. ### 4.5 RF Specifications #### 4.5.1 Frequency Range The MM8108 radio operates in the frequency range from 850 MHz to 950 MHz. #### 4.5.2 Receiver **4.5.2.1 Sensitivity** Sensitivities for 10% packet error rate, 256-byte packets. Conditions are VBAT=3.3 V, 25oC **Table 21: Rate and receiver sensitivity** | MCS Index | Modulation Scheme | Coding Rate | PHY Rate (Mbps) per BW 1 MHz | PHY Rate (Mbps) per BW 2 MHz | PHY Rate (Mbps) per BW 4 MHz | PHY Rate (Mbps) per BW 8 MHz | Minimum Receive Sensitivity (dBm) per BW 1 MHz | Minimum Receive Sensitivity (dBm) per BW 2 MHz | Minimum Receive Sensitivity (dBm) per BW 4 MHz | Minimum Receive Sensitivity (dBm) per BW 8 MHz | | --------- | ----------------- | ----------- | ---------------------------- | ---------------------------- | ---------------------------- | ---------------------------- | ---------------------------------------------- | ---------------------------------------------- | ---------------------------------------------- | ---------------------------------------------- | | 10 | BPSK | 1/2 x 2 | 0.17 | N/A | N/A | N/A | -108 | N/A | N/A | N/A | | 0 | BPSK | 1/2 | 0.33 | 0.72 | 1.5 | 3.3 | -107 | -104 | -102 | -98 | | 1 | QPSK | 1/2 | 0.67 | 1.4 | 3.0 | 6.5 | -105 | -102 | -99 | -96 | | 2 | QPSK | 3/4 | 1.0 | 2.2 | 4.5 | 9.8 | -102 | -99 | -97 | -93 | | 3 | 16-QAM | 1/2 | 1.3 | 2.9 | 6.0 | 13 | -99 | -97 | -94 | -90 | | 4 | 16-QAM | 3/4 | 2.0 | 4.3 | 9.0 | 20 | -96 | -93 | -90 | -87 | | 5 | 64-QAM | 2/3 | 2.7 | 5.8 | 12 | 26 | -92 | -89 | -86 | -83 | | 6 | 64-QAM | 3/4 | 3.0 | 6.5 | 14 | 29 | -91 | -88 | -85 | -81 | | 7 | 64-QAM | 5/6 | 3.3 | 7.2 | 15 | 33 | -89 | -86 | -83 | -80 | | 8 | 256-QAM | 3/4 | 4.0 | 8.7 | 18 | 39 | -85 | -82 | -79 | -76 | | 9 | 256-QAM | 5/6 | 4.4 | N/A | 20 | 43 | -83 | N/A | -78 | -74 | **4.5.2.2 Adjacent Channel Rejection** Adjacent channel rejection is measured by setting the requested signal’s strength 3 dB above the rate-dependent sensitivity specified in 4.5.2.1 and increasing the power of the interfering signal until a 10% PER is achieved for a PSDU length of 256 bytes. The power difference between the interfering and requested channel is the corresponding adjacent channel rejection. **Table 22: Adjacent channel rejection** | MCS Index | Adjacent Channel Rejection (dB) per BW IEEE Spec | Adjacent Channel Rejection (dB) per BW 1 MHz | Adjacent Channel Rejection (dB) per BW 2 MHz | Adjacent Channel Rejection (dB) per BW 4 MHz | Adjacent Channel Rejection (dB) per BW 8 MHz | Non-Adjacent Channel Rejection (dB) per BW IEEE Spec | Non-Adjacent Channel Rejection (dB) per BW 1 MHz | Non-Adjacent Channel Rejection (dB) per BW 2 MHz | Non-Adjacent Channel Rejection (dB) per BW 4 MHz | Non-Adjacent Channel Rejection (dB) per BW 8 MHz | | --------- | ------------------------------------------------ | -------------------------------------------- | -------------------------------------------- | -------------------------------------------- | -------------------------------------------- | ---------------------------------------------------- | ------------------------------------------------ | ------------------------------------------------ | ------------------------------------------------ | ------------------------------------------------ | | 0 | 16 | 25 | 24 | 24 | 25 | 32 | 47 | 48 | 47 | 46 | | 2 | 11 | 17 | 17 | 17 | 18 | 27 | 39 | 41 | 40 | 40 | | 4 | 4 | 11 | 11 | 11 | 12 | 20 | 32 | 34 | 33 | 33 | | 7 | -2 | 1 | 1 | 11 | 2 | 14 | 23 | 24 | 24 | 23 | | 8 | -7 | 0 | -1 | -1 | -2 | 9 | 18 | 21 | 20 | 19 | | 9 | -9 | -1 | N/A | -1 | -1 | 7 | 17 | N/A | 18 | 17 | **4.5.2.3 Maximum Input Power** The following table specifies the maximum input level at RF\_IN for a specified MCS and PER. **Table 23: Maximum receiver input power** | Condition | Max | Unit | | --------------- | --- | ---- | | MCS=0 , PER <1% | 0 | dBm | #### 4.5.3 Transmitter The following transmit power levels are for IEEE compliance for 802.11ah. They do not consider any backoffs needed for regional spectrum compliance (e.g., FCC, IC, TELEC). TX power in edge channels will be limited by the restricted band edge in the regulatory regions. **Table 24: Mean TX output power** | MCS Index | Power output (dBm) at the filter per BW T A =25 o C, V BAT = V DDIO =3.3 V, IEEE-compliant with 1.5 dB SEM margin 1 MHz | Power output (dBm) at the filter per BW T A =25 o C, V BAT = V DDIO =3.3 V, IEEE-compliant with 1.5 dB SEM margin 2 MHz | Power output (dBm) at the filter per BW T A =25 o C, V BAT = V DDIO =3.3 V, IEEE-compliant with 1.5 dB SEM margin 4 MHz | Power output (dBm) at the filter per BW T A =25 o C, V BAT = V DDIO =3.3 V, IEEE-compliant with 1.5 dB SEM margin 8 MHz | | --------- | ----------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------- | ----------------------------------------------------------------------------------------------------------------------- | | 10 | 25.5 | N/A | N/A | N/A | | 0 | 25.5 | 25.0 | 23.0 | 22.5 | | 1 | 25.5 | 25.0 | 23.0 | 22.5 | | 2 | 25.5 | 25.0 | 23.0 | 22.0 | | 3 | 25.5 | 25.0 | 23.0 | 22.0 | | 4 | 24.5 | 24.5 | 22.5 | 22.0 | | 5 | 22.0 | 23.5 | 21.5 | 21.5 | | 6 | 22.5 | 21.5 | 21.0 | 20.5 | | 7 | 19.0 | 20.0 | 20.0 | 20.0 | | 8 | 17.5 | 18.0 | 19.0 | 19.0 | | 9 | 16.0 | N/A | 17.0 | 16.5 | ### 4.6 Digital IO Voltage Specifications **Table 25: Digital IO voltage specifications** | Parameters | Description | VDDIO | Min | Max | Unit | | ----------- | ---------------------------------------------------------------- | ----- | --- | ---- | ---- | | V IL\_VDDIO | Low input threshold for all GPIO and SDIO pins | 3.3 | - | 1.2 | V | | V IH\_VDDIO | High input threshold for all GPIO and SDIO pins | 3.3 | 1.7 | - | V | | V OL\_VDDIO | Low output voltage for all GPIO and SDIO pins, with an 8mA load | 3.3 | - | 0.25 | V | | V OH\_VDDIO | High output voltage for all GPIO and SDIO pins, with an 8mA load | 3.3 | 2.9 | - | V | ## 5 Application Circuit ### 5.1 Schematic Figure 12 shows a reference schematic for the MM8108. Each subcircuit is outlined in the sections below. ![Figure 9: Reference schematic diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/uTYtSzRfZozeP23kRmgU/Unknown%20image) Bypass capacitor values should match those used in the reference design to ensure optimal device operation. Quality X5R or better decoupling capacitors are recommended to ensure stability over temperature and the device's lifetime. The 2.2 uH and 1.5 uH buck inductors pass peak currents of 1 A, therefore, Isat and Itemp must be significantly greater than 1 A for these inductors. High-quality, low-DCR inductors are recommended for stability and reliability. The reference design uses the following buck inductors: * L1 (2.2 uH): Murata DFE201612P-2R2M=P2 * L3 (1.5 uH): Murata DFE201612P-2R2M=P2 Regulating VBAT and VBAT\_TX is essential for performance. For a 500 mA load, VBAT should have less than 10 mV of ripple and 50 mV of load regulation. ### 5.2 Routing information #### 5.2.1 Buck Converter Routing Spacing between the VSW (B9) pin and the inductor (L1) should be minimized, with the inductor and the capacitor of the LC filter placed close to one another. A low-impedance connection from the capacitor ground to the chip ground is required. VBUCK and VBUCK\_TX routing should be short and wide. VBUCK\_FB and VBUCK\_TX\_FB routing should connect nearby to the load pins (VBUCK (A5 & B4) and VBUCK\_TX (G3, H2 & J2) pins, respectively) and do not require wide routing, as these are high-impedance and for voltage sensing feedback only. #### 5.2.2 VBAT Routing VBAT capacitors should be placed as close to the pins as possible with short and wide traces, not routing through vias between the capacitor and the VBAT\_PWR (A8) pin. VBAT routing on the board should have low impedance, and more extended traces should be accounted for with increased capacitance at the pin to avoid VBAT sagging during load events. The capacitance illustrated in the application circuit is the minimal requirement for a well-regulated VBAT supply. If an onboard LDO supplies VBAT, the feedback point should be at the VBAT\_PWR\_TX (J8) load pin or capacitor. If a battery is used to supply VBAT directly, wide traces should be used to provide the best low-impedance path from the battery terminal to VBAT\_PWR\_TX (J8). #### 5.2.3 SPI/SDIO/JTAG Routing Care should be taken to avoid coupling to the RF and buck sections. Impedance matching is unnecessary, but consistent trace widths and spacing are recommended to avoid signal integrity issues, with characteristic impedance not less than 50 Ω to avoid excess capacitive loading. #### 5.2.4 RF Routing Impedance control to 50 Ω is required. Reference designs for TX filter and RX matching can be provided by Morse Micro on request, and complete reference designs with a TR switch can be included. Care should be taken to isolate the RF section from all other parts of the circuit with low-impedance grounding and good spacing. For this purpose, a coplanar waveguide with ground is used in reference designs. It is recommended to minimize impedance discontinuity by routing using components with pad sizes equal to or smaller than the 50 Ω trace. For the same reason, the inter-pad distance should be larger than the 50 Ω trace clearance to the coplanar ground. ![Figure 10: Trace diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/QJ1xtczzxjn2CrikSCqq/Unknown%20image) Component placement should target the shortest overall trace length to minimize losses. ### 5.3 RF Section #### 5.3.1 Transmitter The output is purposefully mismatched away from 50 Ω to optimize power consumption and output power. To meet worldwide regulatory requirements, an external harmonic filter, as shown below, must be included in the design. This filter must be copied precisely, as modification negatively affects efficiency and output power. ![Figure 11: Transmission filter diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/mdf635fEJTzIQcsJRE2n/Unknown%20image) The layout recommendations from Figure 13 apply. The reference design uses the following components: * L6 (4.7 nH): Murata LQP03HQ4N7H02D * C16 (4.3 pF): Murata GRM0335C1H4R3WA01D * L2 (10 nH): Murata LQP03HQ10NH02D * C15 (1.8 pF): Murata GRM0335C1H1R8WA01D #### 5.3.2 Transmit/Receive RF Switch The reference design uses 50 Ω TR switches with low insertion loss and high isolation. Note the requirement for DC-blocking capacitors on the TR switch's RF ports. #### 5.3.3 Receiver Matching The receiver is matched to ensure an optimal balance between noise tolerance and signal sensitivity over the usable bandwidth. The reference circuit will result in optimal performance. ![Figure 12: Receiver matching diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/mVNPigTEXvm4u8r91yo5/Unknown%20image) The reference design uses the following components: * L7 (20 nH): Murata LQP03HQ20NH02D * C17 (2.4 pF): Johanson 250R05L2R4BV4T #### 5.3.4 Antenna/Interstage Matching Interstage matching may be required to minimize losses depending on the antenna, TR switch, and external active components used. Standard techniques are recommended to match each port to an intermediate impedance of 50 Ω. Matching to an intermediate of 50 Ω results in a more robust design since each component can be individually matched to 50 Ω without considering inter-device effects. ## 6 Package Information ### 6.1 Package Dimensions ![Figure 13: Package dimensions](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/i0qMI47enZYdvxVVcwOQ/Unknown%20image) ### 6.2 IC Markings ![Figure 14: IC markings diagram](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/wVuzaoYQrn7sVf3OPxKU/Unknown%20image) **Table 26: IC markings overview** | Line | Marking | Example | Description | | ---- | --------- | --------- | -------------------------------------------------------------------------------------------------- | | 1 | MMXXXXDS | MM8108IB | Device number (XXXX); Optional : Custom marketing letter; Temperature grade (D); Package type (S); | | 2 | TA22 YYWW | TA22 2401 | Fab/Assembly codes; 2 digits for Silicon revision (Major, Minor - Internal Only); date code YYWW; | | 3 | XXXXXXX | 341N001 | Assembly lot number | **Table 27: IC markings details** | Marking | Purpose | Example | Description | | ------- | ---------------------- | ------- | ------------------------------------------ | | M | Major silicon revision | 0..9 | Designated by a single number from 0 to 9 | | N | Minor silicon revision | 0..9 | Designated by a single number from 0 to 9 | | D | Temperature grade | I/C | I = -40 o C to 85 o C; C = 0 o C to 70 o C | | S | Package Type code | Q/B | Q: QFN; B: FCBGA/BGA | ### 6.3 Package Thermal Properties **Table 28: Package thermal properties overview** | Ball count | Size | Power (W) | T A ( o C) | Θ JA ( o C/W) | Θ JC ( o C/W) | Θ JB ( o C/W) | Ѱ JB ( o C/W) | Ѱ JT ( o C/W) | | ---------- | --------- | --------- | ---------- | ------------- | ------------- | ------------- | ------------- | ------------- | | 79 | FCCSP 5x5 | 0.5 | 25 | 31.794 | 6.882 | 7.18 | 1.092 | 1.368 | | 79 | FCCSP 5x5 | 0.5 | 55 | 27.084 | 6.882 | 7.17 | 1.164 | 1.366 | TA: Ambient temperature ΘJA: Thermal resistance junction-to-ambient ΘJC: Thermal resistance junction-to-case ΘJB: Thermal resistance junction-to-board ѰJB: Thermal characterization parameter junction-to-board ѰJT: Thermal characterization parameter junction-to-top (of package) Notes: * JESD51 test standards used * PCB is JEDEC 2S2P test board * Board level solder is SAC405 (thickness = 50 um) * The maximum junction temperature must be controlled to <= 125 °C ## 7 PCB Land Pattern ![Figure 15: PCB land pattern](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/S0srII1QZcLgAm8XZewb/Unknown%20image) **Table 29: PCB land pattern dimensions** | Key | Dimension (mm) | | --- | -------------- | | A | 0.5 | | B | 0.5 | | C | 0.3 | | D | 4.0 | | E | 4.0 | ## 8 Solder Stencil Pattern ![Figure 16: Solder stencil pattern](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/EYTO4EDcRPS55TM06VMq/Unknown%20image) **Table 30: Solder stencil pattern dimensions** | Key | Dimension (mm) | | --- | -------------- | | A | 0.5 | | B | 0.5 | | C | 0.275 | | D | 4.0 | | E | 4.0 | ## 9 Recommended Soldering Profile ![Figure 17: Soldering profile](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/1Hq7oWjuKR6yc9SQLTNU/Unknown%20image) **Table 31: Soldering profile details** | Soldering profile feature | Specification | | -------------------------------------------------------------------------- | ---------------------------------------------------------------------------------- | | Classification temperature (T C ) | 260 °C | | Min soak temperature ( T smin ) | 150 °C | | Max soak temperature (T smax ) | 200 °C | | Time (t s ) from (T smin to T smax ) | 60-120 seconds | | Liquidus temperature (T L ) | 217 °C | | Maximum ramp-up rate (T L to T P ) | 3 °C per second | | Time (t L ) maintained above T L | 60-150 seconds | | Peak package body temperature (T P ) | For users, T P must not exceed the T C For suppliers, T P must equal or exceed T C | | Time (t P ) within 5 °C of the specified classification temperature (T C ) | For users, a maximum of 30 seconds For suppliers, a minimum of 30 seconds | | Maximum ramp-down rate (T P to T L ) | 6 °C per second | | Maximum time 25 °C to peak temperature (T P ) | 8 minutes | Tolerance for peak profile temperature (TP) is defined as a supplier minimum and a user maximum. In other words, if TC is 260 °C and time tP is 30 seconds, this means the following for the supplier and the user: * For a supplier, the peak temperature must be at least 260 °C, and the time above 255 °C must be at least 30 seconds. * For a user, the peak temperature must not exceed 260 °C, and the time above 255 °C must not exceed 30 seconds. All temperatures refer to the center of the package, measured on the package body surface facing up during assembly reflow (live-bug). If parts are reflowed in a different orientation than the normal live-bug assembly reflow orientation (dead-bug), the TP must be within +/- 2 °C of the live-bug TP and still meet the TC requirements; otherwise, the profile shall be adjusted to achieve the latter. To accurately measure peak package body temperatures, refer to JEP140 for recommended thermocouple use. Reflow profiles in this document are for classification/preconditioning and are not meant to specify board assembly profiles. Actual board assembly profiles should be developed based on specific process needs and board designs and within the parameters above. ## 10 Packaging and Labeling ### 10.1 Tray Specifications **Table 32: Tray specifications** | Term | Definition | | --------------- | ------------------------ | | Product | MM8108 | | Number of units | 490 | | Tray size | 322.6 mm x 135.9 mm | | Vacuum seal | Yes | | Dry bake | 125 o C / 24 hours (ML3) | | Pin 1 indicator | Marked on the chip | ![Figure 18: Tray specifications](https://content.gitbook.com/content/C7zRQJQJws9WxgXTA97e/blobs/qbMmCRYCvhlDRAuur3k5/Unknown%20image) ## 11 Handling and Storage The MM8108 IC is a moisture-sensitive device rated at Moisture Sensitive Level 3 (MSL3) per IPC/JEDEC J-STD-20. After opening the moisture-sealed storage bag, ICs that will be subjected to reflow solder or other high-temperature processes must be: 1. Mounted to a circuit board within 168 hours at factory conditions (≤ 30 °C and < 60 % RH) OR 2. Continuously stored per IPC/JEDEC J-STD-033 ICs exposed to moisture and environmental conditions exceeding packaging and storage conditions must be baked before mounting according to IPC/JEDEC J-STD-033. Failure to meet packaging and storage conditions will result in irreparable damage to chips during solder reflow. ## 12 Part Number and Ordering Information **Table 33: Part number and ordering information** | Part Number | Packing Type | M OQ and Order Multiples | Package | Description | Operating Ambient Temperature | | ----------- | ------------ | ------------------------ | --------------- | ----------------------------------------------------------------------------------------------------------------------- | ----------------------------- | | MM8108IB-T | Tray | 490 | BGA 5 mm x 5 mm | Multi-region Wi-Fi HaLow / IEEE 802.11ah Sub-1 GHz SoC with USB Interface and Integrated Power and Low Noise Amplifiers | -40 °C to 85 °C | | MM8108IB-TR | Tape & Reel | 3000 | BGA 5 mm x 5 mm | Multi-region Wi-Fi HaLow / IEEE 802.11ah Sub-1 GHz SoC with USB Interface and Integrated Power and Low Noise Amplifiers | -40 °C to 85 °C | ## 13 Revision History | Release Number | Release Date | Release Notes | | -------------- | ------------ | ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | Version 4 | 18 Sep 2025 | Updated formatting Update pin descriptions Updated power management Updated timing graphs Updated electrical specifications Updated RF specifications Added digital IO specifications Added PCB land solder stencil patterns | | DS102 | 8 Jan 2025 | General update | | DS101 | 4 Nov 2024 | Add packaging and handling information Add soldering information Add labeling information | | DS100 | 1 Nov 2024 | Initial release | Morse Micro provides this information "as is" without warranties of any kind, express or implied. No guarantee is made as to the accuracy, completeness, or suitability of this information or Morse Micro’s products for any specific purpose. Use of this information and products is at the user’s sole risk. Morse Micro products are not designed or tested for use in mission-critical systems, and should not be used in such applications. Performance specifications are based on internal testing and are believed to be reliable; however, they are not guaranteed. It is the Buyer’s responsibility to test and validate all product performance, compatibility, and compliance, both in isolation and within end applications. Morse Micro assumes no liability for the use or application of any product, circuit, or information described herein. No license or other rights—express or implied—are granted under Morse Micro’s intellectual property. This document contains proprietary information of Morse Micro and is subject to change without notice. Wi-Fi®, Wi-Fi HaLow™, and the Wi-Fi logo are trademarks of Wi-Fi Alliance. ZigBee™ and Z-Wave™ are trademarks of their respective owners. All other trademarks are the property of their respective owners.