> For the complete documentation index, see [llms.txt](https://docs.morsemicro.com/llms.txt). Markdown versions of documentation pages are available by appending `.md` to page URLs; this page is available as [Markdown](https://docs.morsemicro.com/design-guides/mm8108-mf15457-hardware-design-guide.md). # MM8108-MF15457 Hardware Design Guide [Download as PDF](https://www.morsemicro.com/resources/design_packages/MM8108-MF15457_Hardware_Design_Guide.pdf) ## 1 Introduction The MM8108-MF15457 is a sub-GHz transceiver system-on-module (SoM) designed for long-range, low-power wireless communication using the IEEE 802.11ah standard. It integrates RF baseband, medium access control (MAC), and digital interfaces into a compact, low-power device optimized for embedded and Internet of Things (IoT) applications. The purpose of this document is to guide hardware integration of the MM8108-MF15457 into custom designs. It covers practical essentials, including power delivery, RF layout, and digital interfaces, to help engineers design products integrating HaLow Wi-Fi. This guide does not cover regulatory certification, application software, or system-level networking architecture. The following sections will focus on implementation details that are typically beyond the scope of high-level documentation. The goal is to complement the datasheet and reference designs by clarifying key layout, functional, and interface considerations relevant to hardware design. ## 2 System Planning and Preparation Time to market depends not only on design choices but also on the order in which they are made. Sequencing tasks so that items with upstream dependencies start early ensures that the necessary information is available when needed. When fundamental details regarding component selection, layout constraints, or system requirements are left unresolved until later, this can lead to redesigns or delays. Resolving these upfront prevents unnecessary blocking of progress. ### 2.1 Impedance Control Contact the PCB manufacturer early in the design process to obtain their recommended coplanar waveguide trace geometry, based on the dielectric constant, loss tangent, and dielectric thickness of their process. The MM8108-MF15457 is designed for 0.6 mm wide traces with 0.4 mm spacing, which makes a 50 Ω characteristic impedance achievable on a 2-layer board; however, a closely spaced ground plane will significantly reduce the need for tapering the main RF trace connection to the module, meaning that a 4-layer stackup can offer signal integrity benefits over a 2-layer design. For FR-4 fiberglass substrate, the thickness of the dielectric between the top copper and ground plane should be in the order of 0.2 mm to 0.4 mm. PCB trace geometry is often limited by the smallest-pitch component in the RF chain. It is advisable to identify these key RF components early and base the impedance-controlled layout around them. Components and connectors with pad widths near 0.6 mm are preferred, as they help minimize impedance mismatches caused by trace-width variation. Impedance calculation tools and formula-based estimators may be useful for approximating trace dimensions. However, these models are not necessarily derived from exact field solutions; many are empirical or quasi-empirical curve fits to simulation and measurement data. Manufacturers typically apply their own field solvers and impedance tuning, so collaboration with them is essential. Coordination with your PCB manufacturer should ideally occur before layout begins; otherwise, you may have to redo routing if trace geometries need to be adjusted later. When using multiple vendors, unique trace geometries are usually required for each vendor. Advanced simulation tools (full-wave 3D solvers) offer greater accuracy than equation-based methods by accounting for geometry, material variation, and board-specific features. This level of modeling is warranted when losses or impedance variations of less than 1 dB are significant to the application. ### 2.2 Component Availability Verify the long-term availability and lead times for critical components early in the design process. This ensures your product’s lifecycle won’t be jeopardized by supply issues or sudden obsolescence. Application examples are provided in Section 6 of this guide. These examples include component lists that may be used as proxies for budgetary purposes or followed directly if the design example matches your application. It can be helpful to address availability risks for rare or non-substitutable parts early in the design process, while deferring broader component ordering until after the PCB has been released for fabrication. This approach is applicable when component lead times are shorter than the PCB turnaround time, allowing part procurement to proceed in parallel with PCB fabrication. ### 2.3 Antenna Selection The antenna will both influence and be influenced by the final enclosure design, which, at the time of hardware design, is likely still evolving. An antenna’s performance depends heavily on its immediate surroundings, including the enclosure, internal cabling, external cabling, nearby metallic structures (including the PCB), and objects in the deployment environment. These factors should be kept in mind throughout the design process to avoid costly redesigns if performance issues are discovered late. It is advisable to obtain antenna samples and begin testing early, even while PCB design is underway. Return loss and radiation pattern (gain vs angle) should be measured using a setup that approximates the final enclosure and cabling. Be aware that changes to your enclosure, cables, or the surrounding environment may require a change in antenna selection, yet those elements themselves depend on a PCB layout that is still in development. This interdependency must be managed throughout development. #### 2.3.1 Antenna Connectors If the product interfaces with a standard 50 Ω RF connector (as opposed to an integrated PCB antenna), there are no specific preparation tasks to complete before design commences. The PCB designer's focus should be on maintaining a consistent 50 Ω impedance throughout the RF path using best-practice layout techniques. System-level testing should be considered early, as interactions among the antenna, enclosure, cabling, and nearby conductive structures will influence performance and shape choices regarding antenna type, connector placement, and enclosure design. #### 2.3.2 Off-The-Shelf Antennas When selecting an off-the-shelf antenna for a Wi-Fi HaLow (IEEE 802.11ah) module, it is critical to ensure compatibility with the sub-GHz frequency range (typically 860 to 930 MHz, depending on the region) and a bandwidth of at least 8 MHz (depending on the region). Wi-Fi HaLow operates on a wider bandwidth than other common ISM-band technologies (such as LoRa), so care must be taken to check the antenna's operating bandwidth if it is advertised for use with one of these other technologies. For general-purpose deployment and consistent coverage, a dipole antenna is recommended due to its omnidirectional radiation pattern in the azimuth plane. This facilitates uniform signal strength around the antenna, which is ideal for applications where client devices can be readily distributed. Key parameters to consider include antenna gain (typically 1 to 3 dBi for dipoles), connector type (must match the end-product’s or module’s RF interface), mechanical form factor, and environmental rating. #### 2.3.3 Electrically Small Antennas At 915 MHz, antennas shorter than approximately 30 mm are considered electrically small. Designs in this range are especially difficult, with significant trade-offs in efficiency, bandwidth gain, and susceptibility to detuning from nearby materials. More generally, any antenna smaller than a quarter wavelength (approximately 80 mm) should be approached with caution. As physical size decreases below this point, impedance matching becomes more sensitive, performance becomes less predictable, and it becomes more dependent on enclosure design and nearby conductors. Early validation and testing are strongly recommended for antennas below this size threshold. Plan for extensive impedance matching, validation, and possibly iterative tuning of the matching network and physical layout to ensure acceptable performance. #### 2.3.4 PCB Antennas The performance of a PCB antenna design depends on the manufacturing process, PCB material, enclosure, cabling, and other nearby structures. Design parameters, such as the required gain for the PA and LNA, and the recommended matching topology, are best determined with knowledge of the antenna’s impedance and radiation characteristics. It is recommended to plan to design and build early prototypes specifically for antenna evaluation, even before laying out the full product. These can include the enclosure, dummy connectors, cabling, and the antenna section, while omitting other circuitry. Such setups enable return-loss and antenna-pattern measurements that put the design in the right ballpark. While further adjustments may be expected, this process reduces uncertainty and enables more informed decisions before significant investment in the final layout. ## 3 Module Pinout This section provides the details required to create a PCB footprint and schematic symbol for the MM8108-MF15457. It includes a visual overview of the module land pattern and a table of pin functions. ### 3.1 Component Land Pattern Square pads of uniform size and spacing are recommended. ![Figure 1: Land pattern for the MM8108-MF15457 module](/files/728cdeeada01a6c4ee488990b805c602eb6f89c2) *Figure 1: Land pattern for the MM8108-MF15457 module* Dimensions are provided in mm. Alternative dimensions in mil (thou) have been provided for convenience. Where ambiguity exists (due to rounding, for example), the mm dimensions should be treated as the source of truth. | | | | | ---------------- | -------------- | --------------- | | Key | Dimension (mm) | Dimension (mil) | | Package X | 11.0 | 433 | | Package Y | 10.0 | 394 | | Pad X | 0.6 | 24 | | Pad Y | 0.6 | 24 | | Pad Spacing X | 1.0 | 39 | | Pad Spacing Y | 1.0 | 39 | | Package to Pad X | 0.5 | 20 | | Package to Pad Y | 0.5 | 20 | **Table 1: Key Dimensions associated with Figure 1** ### 3.2 Schematic Symbol The diagram below shows a top view of the module package with each pin numbered and labeled. Pins are numbered clockwise around the package. Signal names are annotated alongside each pin. ![Figure 2: Diagram showing pinout information for the MM8108-MF15457 module](/files/55c0e61b9cf262d06831e0d7855946f53088bfc3) *Figure 2: Diagram showing pinout information for the MM8108-MF15457 module* An example schematic element is provided below, with pins approximately grouped by function. ![Figure 3: Schematic symbol showing pinout information for the MM8108-MF15457 module](/files/5996bfe6f115e48b8ad8ea0a5255eca9f458da2b) *Figure 3: Schematic symbol showing pinout information for the MM8108-MF15457 module* The table below lists all pads, along with their signal names, electrical types, and functional descriptions. The "Type" column identifies each signal’s role, such as an analog interface, a power supply, or a ground return, to support interpretation during circuit design and layout. Descriptions are included to clarify functionality, particularly where the signal name alone may not indicate intended use. | | | | | | | --- | --------- | ----------- | --------------------------------------------- | ----------- | | Pin | Name | Type | Function | Alternative | | 1 | GND | Ground | Ground | | | 2 | ANT | Analog | Antenna | | | 3 | GND | Ground | Ground | | | 4 | RESET\_N | Digital I/O | Asynchronous chip reset (active low) | | | 5 | WAKE | Digital I/O | External wake from Deep Sleep and Snooze | | | 6 | JTAG\_TMS | Digital I/O | JTAG Mode Select | GPIO15 | | 7 | JTAG\_TCK | Digital I/O | JTAG Clock | GPIO13 | | 8 | JTAG\_TDO | Digital I/O | JTAG Data Out | GPIO16 | | 9 | JTAG\_TDI | Digital I/O | JTAG Data In | GPIO14 | | 10 | VDD | Supply | 3.3V Supply | | | 11 | GND | Ground | Ground | | | 12 | SDIO\_D0 | Digital I/O | SDIO Data Line | SPI\_MISO | | 13 | SDIO\_D3 | Digital I/O | SDIO Data Line | SPI\_CS | | 14 | SDIO\_D1 | Digital I/O | SDIO Data Line | SPI\_INT | | 15 | SDIO\_D2 | Digital I/O | SDIO Data Line | | | 16 | SDIO\_CMD | Digital I/O | SDIO Command Line | SPI\_MOSI | | 17 | SDIO\_CLK | Digital I/O | SDIO Clock Input | SPI\_SCK | | 18 | GPIO5 | Digital I/O | Programmable digital I/O | | | 19 | GPIO4 | Digital I/O | Programmable digital I/O | | | 20 | GND | Ground | Ground | | | 21 | GPIO3 | Digital I/O | Programmable digital I/O | | | 22 | VDDIO | Supply | Host Supply for digital I/O | | | 23 | GND | Ground | Ground | | | 24 | VDD\_TX | Supply | 3.3V Supply | | | 25 | VDD\_USB | Supply | 3.3V USB Supply | | | 26 | GND | Ground | Ground | | | 27 | USB\_DN | Digital I/O | USB D- Line | | | 28 | USB\_DP | Digital I/O | USB D+ Line | | | 29 | BUSY | Digital I/O | The module is transmitting or processing data | | | 30 | GND | Ground | Ground | | | 31 | GPIO1 | Digital I/O | Programmable digital I/O | | | 32 | GPIO0 | Digital I/O | Programmable digital I/O | | | 33 | GPIO6 | Digital I/O | Programmable digital I/O | | | 34 | GPIO7 | Digital I/O | Programmable digital I/O | | | 35 | GPIO8 | Digital I/O | Programmable digital I/O | | | 36 | GPIO9 | Digital I/O | Programmable digital I/O | | | 37 | GPIO10 | Digital I/O | Programmable digital I/O | | | 38 | GND | Ground | Ground | | **Table 2: MM8108-MF15457 pin descriptions** ## 4 Schematic Design An example schematic design is shown below. It includes all critical components for a typical MM8108-MF15457 design. ![Figure 4: Typical application schematic for the MM8108\_MF15457 and surrounding circuitry](/files/69ecb7ac5c19817fa5dfd6252c7b74294a3339d3) *Figure 4: Typical application schematic for the MM8108\_MF15457 and surrounding circuitry* A recommended schematic design workflow is to begin with the RF signal path, followed by the USB signal path. Once these are in place, complete the power supply, decoupling capacitors, I/O configuration, diagnostics, and protection circuitry. ### 4.1 Radio Frequency The RF section should be the primary design consideration. It is the device's core functionality and one of the more challenging aspects of the design. #### 4.1.1 Impedance Control RF nets between the module and antenna should be designated as impedance-controlled (50 Ω characteristic impedance) in the schematic editor to ensure that the correct routing constraints are applied during layout. #### 4.1.2 Antenna and Associated Matching If an off-the-shelf 50  Ω antenna is used (or the RF output is simply routed to a 50  Ω connector), then matching is not required; the best performance is achieved by routing directly, with a short trace from the RF output to the connector. However, many designers choose to include a placeholder pi or tee network. This introduces a performance trade-off (wider pads, extra trace length, and additional components leading to added mismatch, loss, and cost) in exchange for the flexibility that, if issues arise later in the development process, these footprints may allow for filtering or attenuation. ![Figure 5: A pi network](/files/9a99d4841d94144dd80ac9f1c57031c49cece7d7) *Figure 5: A pi network* If the antenna is not 50 Ω (as is often the case with electrically short PCB antennas), impedance matching becomes mandatory. A generic pi or tee network can be included to facilitate matching, which poses minimal effort for a roughly matched system. However, the optimal matching circuitry will depend on the antenna's exact impedance, including the PCB, the enclosure, and the deployment scenario. It is advisable to produce antenna-only PCB prototypes and utilize a VNA to measure the system performance; this data will be needed to implement optimized front-end matching. Antenna Design Considerations: When designing a small-form-factor PCB antenna, changes in antenna geometry will affect the load presented by the antenna (i.e., the unmatched antenna). To the extent this may be influenced by design decisions, the top region of the Smith chart is recommended (Figure 6), as it can be matched purely capacitively, which behaves more ideally (exhibiting less loss and less magnetic coupling) than inductive matching. ![Figure 6: Target impedance region on the Smith chart for small-form-factor PCB antennas](/files/8a0c7340b75e4417ab71c1981a6600628885350a) *Figure 6: Target impedance region on the Smith chart for small-form-factor PCB antennas* ### 4.2 Radio Frequency Front End For most applications, the only component required at the antenna port is a single 50 Ω antenna operating from 902 MHz to 928 MHz (or 863 MHz to 868 MHz in the EU). Advanced applications may wish to apply additional circuitry, the discussion of which is outside the scope of this hardware design guide. ### 4.3 Universal Serial Bus The USB design considerations are discussed here (rather than in Section 4.6) so that USB signals are considered early and given high design priority. Signal integrity considerations for USB should be addressed early in the design process to produce a more reliable and robust product. You should treat the USB signals as the second priority, where RF traces are the highest priority. An example schematic layout for USB host interfacing is provided below: ![Figure 7: USB host interface to the MM8108-MF15457](/files/69ecb7ac5c19817fa5dfd6252c7b74294a3339d3) *Figure 7: USB host interface to the MM8108-MF15457* USB nets between the module and connector must be designated as length-matched to within 100 ps (where 1 mm is recommended) and impedance-controlled (90  Ω differential characteristic impedance) in the schematic editor to ensure the correct routing constraints are applied during layout. For USB-C, the CC lines should be designated as impedance-controlled (50 Ω characteristic impedance), and these signals should receive particular attention to schematic design elements that may produce reflections on the signal line. ⚠️USB signal integrity issues can be particularly hard to find because they often result in subtle non-specific error modes such as slower data rates or intermittent unexpected behavior; as such, it is recommended that they be designed with best practice principles to avoid difficulty later. Specific care should be taken when placing any components in series with the USB lines (such as ESD protection or switching). These components must be specifically designed for USB 2.0 applications, as general-purpose components can significantly degrade USB signal integrity. ### 4.4 Decoupling Capacitors The VDD, VDD\_TX, and VDD\_USB pins should be decoupled with 10 μF and 100 nF ceramic capacitors, each rated for at least 6.3 V. Either X7R or X5R capacitors are recommended. ![Figure 8: Decoupling capacitors required for VDD, VDD\_TX, and VDD\_USB](/files/9c53432c95ff04adae3dcdede8c0f1b8181ad290) *Figure 8: Decoupling capacitors required for VDD, VDD\_TX, and VDD\_USB* ![](/files/2241896cd5723b170f895610da9d6a543faa0587) ![](/files/9a2133d34818132fd177f83dc2da921b750e0fe4) The VDDIO pin should be decoupled with a 100 nF ceramic capacitor, rated for at least 6.3 V. Either X7R or X5R capacitors are recommended. ![Figure 9: Decoupling capacitor required for VDDIO](/files/c904d4b8ae218b6a515ff456016ae52799cc4417) *Figure 9: Decoupling capacitor required for VDDIO* ⚠️Note: the effective capacitance of ceramic capacitors can drop significantly under applied DC bias, especially in smaller packages. For example, a nominal 4.7 µF capacitor in a 0402 package may deliver less than 2 µF at 3.3 V. When selecting capacitors for bulk storage, consult the manufacturer’s bias derating curves to ensure that sufficient capacitance remains available under load. If necessary, use a larger case size or a higher voltage rating to reduce the percentage loss. ### 4.5 Power Supply The performance of the MM8108-MF15457 depends critically on the quality and stability of its power supply. While the device includes internal regulators to generate the required internal voltages, it is sensitive to droop, ripple, and noise on the primary voltage supply. ![Figure 10: Simplified system block diagram showing power path](/files/fa6593b2b534e0b2c22c5395d5235b10357076c6) *Figure 10: Simplified system block diagram showing power path* The voltage supply should remain within the 3.0 to 3.6V range across all load conditions (from sleep currents to peak TX current) and under expected variations in input supply. Gradual shifts in the power supply voltage (e.g., from a discharging battery) are tolerated by the internal LDO and buck converters. However, high-frequency noise on the supply remains a critical consideration for RF performance. Note that VDDIO is tolerant of voltages as low as 2.25 V. Appropriate level-shifting circuitry must be used when interfacing with systems operating at lower voltages (such as 1.8 V). The MM8108-MF15457 is typically powered by an external voltage regulator, which should have an output ripple below 30 mV peak-to-peak and supply at least 500 mA continuously. If a switch-mode power supply is used, it is strongly recommended to include a footprint for an RF shielding can that fully encloses its perimeter. This allows a shield to be fitted, if required, to suppress radiated emissions and preserve receiver sensitivity. ### 4.6 Interfacing #### 4.6.1 USB Universal serial bus signal integrity considerations are discussed in Section 4.3. #### 4.6.2 SDIO / SPI The MM8108-MF15457 supports SDIO and SPI communication (depending on which firmware is loaded). Information about the hardware pin configuration is given in the following table. | | | | | | | --- | --------- | ----------------- | --------------- | --------- | | Pin | Name | SDIO 4-bit mode | SDIO 1-bit mode | SPI mode | | 12 | SDIO\_D0 | Data pin 0 | Data pin | SPI\_MISO | | 13 | SDIO\_D3 | Data pin 3 | - | SPI\_CS | | 14 | SDIO\_D1 | Data pin 1 | IRQ | SPI\_INT | | 15 | SDIO\_D2 | Data pin 2 | - | 1 | | 16 | SDIO\_CMD | Command pin | | SPI\_MOSI | | 17 | SDIO\_CLK | Clock pin (input) | | SPI\_SCK | **Table 3: Pinout for SPI and SDIO interfacing** 1 In SPI mode, SDIO\_D2 must be pulled high via an external pullup resistor. ⚠️ Note: A typical SPI clock speed is 25 MHz. Take extra care if any clocks in your design operate at or near this frequency. The 37th harmonic of 25 MHz is 925 MHz, which falls within the sub-1 GHz bands used by Wi-Fi HaLow. ⚠️ Morse Micro doesn't recommend SPI bus sharing with other peripheral devices. **4.6.2.1 SPI** An example schematic layout for SPI host interfacing is provided below. ![Figure 11: SPI host interface to the MM8108-MF15457](/files/b74cf451854a910af70c89cc4b082adac7e212e3) *Figure 11: SPI host interface to the MM8108-MF15457* When selecting a host to interface with the MM8108-MF15457 module via the SPI interface, consider the following recommendations to achieve the best throughput: * The host must support level-triggered interrupts. * The host must support full-duplex SPI mode. * The host must support DMA-backed transactions on the SPI bus. Standard SPI can achieve up to 25 Mbps at 50 MHz, but without DMA support, performance will be significantly reduced. For example, an SPI interface with an 8-byte buffer per transaction might achieve only 2 Mbps of throughput on the SPI bus. For proper operation and to take advantage of the module’s power-saving features, connect RESET\_N and WAKE to standard digital outputs (CMOS logic levels). The BUSY signal should be connected to a digital input (also CMOS-level). Do not use open-collector or open-drain circuits, as they will cause incorrect behavior. **4.6.2.2 SDIO** An example schematic layout for SDIO host interfacing is provided below. ![Figure 12: SDIO host interface to the MM8108-MF15457](/files/0e7bf9697da101e97bbdc10d99aacd78632a7b0a) *Figure 12: SDIO host interface to the MM8108-MF15457* The SDIO\_CLK line must not include a pull-up resistor. The remaining SDIO lines (SDIO\_CMD, SDIO\_D0, SDIO\_D1, SDIO\_D2, and SDIO\_D3) must be pulled up to VDDIO with 10 kΩ to 100 kΩ resistors. The responsibility for providing these resistors falls on the host side; however, if the host does not provide them or their implementation is uncertain, it is acceptable to place the resistors on the peripheral side (the MM8108-MF15457) to ensure correct logic levels. SDIO traces should be routed with 50 Ω characteristic impedance. Basic length matching to within 10 mm is also required. If signal integrity issues are observed, such as excessive trace length or overshoot, series damping resistors in the range of 10 Ω to 100 Ω may be beneficial. When signal behavior is unknown at design time, footprint provisions for 0 Ω resistors can be included to preserve the option to correct signal-integrity issues discovered during verification. As a layout best practice, place SDIO devices close enough that transient pulses arising from any impedance mismatch will resolve well within a clock cycle. It is recommended that the SDIO trace length be kept under 50 mm to minimize signal integrity concerns. ![Figure 13: Placeholder series damping resistors for SDIO](/files/9070b5c79a30c347d09a3230a7bd9e344fe80a13) *Figure 13: Placeholder series damping resistors for SDIO* When multiple host controllers are supported through different build options, it is critical to include explicit 0 Ω resistors (or similar jumpers) to disconnect unused signal paths from the SDIO lines. Simply leaving an unused host controller interface unpopulated is not enough; the signal traces should be physically isolated to prevent unterminated stubs that can cause signal reflections and degrade SDIO signal integrity. ![Figure 14: Selection of SDIO host controller via 0 Ω resistors](/files/bec32ff844031cfdcebac74fc238d447b9107892) *Figure 14: Selection of SDIO host controller via 0 Ω resistors* For host controllers operating at IO below 2.5 V, level shifters are recommended when interfacing with the MM8108-MF15457. Figure 15 demonstrates an example circuit layout using the Texas Instruments TXS02612, which can level-shift SDIO signals down to 1.1V. ![Figure 15: SDIO level shifting circuit](/files/e647af3b647c0daa06b21ae5d622c11142642c7b) *Figure 15: SDIO level shifting circuit* #### 4.6.3 GPIO GPIO may be used in specialized applications and are not user-programmable. Most GPIO signals operate at low speeds and do not typically require strict routing constraints for signal integrity. However, in applications with high edge rates, attention should be paid to trace length, return-path continuity, and termination. **4.6.3.1 WAKE Pin Considerations** The wake pin allows an input signal into MM8108-MF15457 to bring the module out of deep sleep and snooze modes. This is part of the VDD analog domain and cannot be driven by anything below 3.0 V. Caution is required when the host controller operates with VDDIO below 3.0 V to ensure appropriate level-shifting is used when driving WAKE. **4.6.3.2 RESET\_N Pin Considerations** The active-low reset pin should be connected to a power-on reset network consisting of a 220 kΩ pull-up resistor and a 2.2 µF capacitor to ground. This ensures that the MM8108-MF15457 is properly initialized upon power-up. The RESET\_N pin can also be driven low by an external device to reset the device. ### 4.7 Diagnostics #### 4.7.1 Preferred Diagnostics For robust design and enhanced troubleshooting capability, it is advisable to include a 16-pin header (Morse Micro uses the Samtec FTSH-108-01-F-D-K) with the pinout shown below to enable diagnostic access. ![Figure 16: Standard pinout for diagnostics connector](/files/1f4e202c375acf1ea0ca971813729423cf012617) *Figure 16: Standard pinout for diagnostics connector* The following pin configurations are recommended: | | | | | --- | -------------- | ------------------------------ | | Pin | Net | Description | | 1 | VDDIO | Digital domain power rail | | 2 | GND | Ground | | 3 | MM\_JTAG\_TDI | JTAG TDI | | 4 | MM\_JTAG\_TDO | JTAG TDO | | 5 | MM\_JTAG\_TCK | JTAG TCK | | 6 | MM\_JTAG\_TMS | JTAG TMS | | 7 | MM\_JTAG\_TRST | JTAG Test Reset (Not required) | | 8 | MM\_RESET\_N | Device Reset | | 9 | MM\_GPIO2 | Debug | | 10 | MM\_GPIO3 | Debug | | 11 | MM\_SD\_CLK | SPI CLK | | 12 | MM\_SD\_CMD | SPI MOSI | | 13 | MM\_SD\_D0 | SPI MISO | | 14 | MM\_SD\_D3 | SPI CS | | 15 | - | Not connected | | 16 | MM\_WAKE | Wake up | **Table 4: Standard pinout for diagnostics connector** #### 4.7.2 Reduced Diagnostics In designs where a full diagnostics header is not feasible, a reduced interface is supported. This consists of a 10-position 1.27mm pitch connector with the following connections: ![Figure 17: Pinout for alternative diagnostics connector](/files/5786c3125e5721b466f8ac1d1e299a5e682b5d96) *Figure 17: Pinout for alternative diagnostics connector* ![](/files/56cf7bd1c3daf2c83158233f5be2329431067a62) A diagnostics port is not required for normal device operation. However, if no debug access is provided in the design, Morse Micro's ability to support, diagnose, or resolve technical issues will be reduced. ### 4.8 Protection This section refers to protection against unexpected conditions, such as electrostatic discharge (ESD), reverse polarity, overvoltage, overcurrent, brownout, etc. Standard best-practice ESD protection is recommended on all nets exposed to the external environment. This includes placing protection at the outermost connectors rather than directly at the MM8108-MF15457 pins. Avoiding ESD components on the RF trace helps preserve signal integrity by minimizing parasitic shunting and impedance discontinuities. For the antenna trace in particular, 1 kV of ESD protection is already provided by the module. If additional ESD protection is required, the selected TVS diode must have an input capacitance less than 0.2 pF, and its footprint should preserve controlled-impedance geometry without introducing abrupt transitions on the PCB RF trace. The MM8108-MF15457 is rated for 3.0 to 3.6 V. For nominal operation at 3.3 V, clamping the supply voltage to 3.4 to 3.6 V is sufficient to protect the device from supply transients. The module does not include reverse-polarity protection, so this must be implemented externally in systems where reverse polarity may occur (for example, when a user inserts a battery backward). When adding voltage clamping or reverse-polarity protection to a design, consider any trade-offs, such as increased leakage current. This is particularly important for low-power or battery-operated applications, where minimizing power consumption is critical. ## 5 PCB Layout The following sections of this guide are organized to match the recommended workflow for a PCB layout engineer, addressing each area in turn, starting with placement, then routing, from the most critical elements (RF) down to the least (GPIO). By completing one section before moving to the next, this process naturally ensures that the most important parts receive the most favorable design trade-offs. ### 5.1 Radio Frequency The RF section should be the primary consideration in the layout. It’s recommended to route it first to ensure it naturally receives the most favorable design trade-offs. #### 5.1.1 Placement Guidelines It is advisable to start by placing the antenna, followed by any other RF components (if applicable), and then the Wi-Fi HaLow transceiver module. This allows the RF section to be tightly packed with short, direct traces. During this process, many design trade-offs will emerge. The following section outlines the key considerations when placing the RF components. **5.1.1.1 Path Length** Place RF components close to keep traces as short as possible. This will reduce insertion loss, improve transient settling, and minimize electromagnetic interference. Longer traces introduce greater resistive and dielectric loss, which reduces efficiency. A shorter trace also limits the round-trip path for reflections, allowing signals to settle more quickly after a transition. Shorter paths reduce the physical aperture available for radiated emissions or coupling to adjacent circuitry. As a guideline, RF traces should be kept significantly shorter than one-tenth of the signal wavelength in the PCB dielectric. For typical coplanar waveguide or microstrip traces on FR4 at 915 MHz, this corresponds to approximately 15 mm. Traces longer than this threshold require greater attention to impedance control and layout. However, minimizing length is beneficial in all cases: Ohmic and dielectric losses scale directly with trace length, and even short traces exhibit improved efficiency and reduced insertion loss. **5.1.1.2 Current Loops** Orient and place components that connect to ground (like decoupling capacitors or terminations) so their ground pads are as close as possible to vias or traces leading to the ground plane. Minimize the area enclosed by the signal and its return path, as this reduces loop inductance and magnetic coupling. Component placement should ensure that PCB traces are not routed beneath the antenna, RF feedline, and any other RF front-end circuitry. **5.1.1.3 Separation from Noise Sources** Keep RF components and traces well separated from all other circuitry. As a general guideline, maintain at least 10 mm of clearance from other components and traces, and maximize the distance from switching regulators, high-speed digital lines, and potential electromagnetic interference sources. Layout choices should prioritize clean isolation, especially in sensitive receive paths or matched impedance networks, because even low-level coupling can degrade performance. It is advisable to define explicit keep-out zones around RF traces, matching networks, and the RF front-end module to prevent electromagnetic coupling and preserve circuit isolation. **5.1.1.4 Parasitic Impedances** When placing RF components, remember that PCB traces introduce parasitic inductance, while component pads add parasitic capacitance. Extra trace length is generally less critical for inductors, just as added copper area has less impact on capacitors. Knowing in advance whether a matching network will require inductors or capacitors (rather than relying on generic pi or tee footprints) allows placement and routing to minimize parasitic inductance at capacitors and parasitic capacitance at inductors. **5.1.1.5 Inductor Considerations** Careful placement and orientation of inductors is essential to minimize magnetic coupling, which can degrade RF performance or inject noise into sensitive circuits. When multiple inductors are used in close proximity (such as RF matching inductors and DC-DC converter inductors), their coils should be oriented orthogonally. Avoid placing inductors with parallel coil axes, as this maximizes coupling. Maintaining physical separation between inductors further reduces the risk of coupling. These considerations are especially important during RF reception, when the system is most sensitive to low-level noise. In this state, any coupling between switching inductors and RF paths can compromise receiver performance. In particular, inductors inside matching circuits can act as antennas that pick up radiated noise. **5.1.1.6 Matching Component Considerations** Matching components should be placed as close as possible to the unmatched element (e.g., the antenna). PCB traces before (or between) the matching components should not be viewed as conventional 50 Ω transmission lines, so keeping these traces to a minimum length reduces unwanted impedance transformation. Some advanced matching techniques may intentionally introduce phase shifts using this approach; however, such techniques are outside the scope of this guide. **5.1.1.7 PCB Antenna Considerations** Follow the antenna manufacturer’s recommended keep-out dimensions carefully and measure antenna performance (including return loss and radiation pattern) as part of the design process. Keep in mind that PCB layout, nearby structures, and the enclosure can significantly influence antenna behavior, and the specific interactions of your product are not captured in the antenna datasheet. **5.1.1.8 Shielding Considerations** The MM8108-MF15457 comes with an RF shielding can over the RF circuitry, and additional Wi-Fi HaLow RF shielding is usually not required, except in advanced applications. Switch-mode power supplies may require additional shielding cans. Keep in mind that inductors are particularly prone to radiating and receiving noise, and during RF receive, even low-level coupled noise can degrade sensitivity or introduce spurious responses. The shield should fully enclose the sensitive region, with a solid via-stitched ground perimeter to ensure good RF sealing. Large openings or poorly grounded shields can significantly compromise effectiveness. The primary purpose of shielding is to prevent emissions from other system components (particularly high-speed digital switching, or RF) from coupling into the antenna path and degrading receiver sensitivity. The device can detect down to –107 dBm, so even very weak internal emissions can raise the noise floor and limit system performance. Effective shielding should form a continuous seal. The limiting factor in shielding effectiveness is typically the largest dimension of any aperture or discontinuity in the shield, not the overall coverage percentage. Shielding with large openings often provides little benefit and can introduce resonances or coupling paths that degrade performance. At 915 MHz (λ ≈ 328 mm), the reactive near field extends approximately 50 mm from any source of interference. Within this region, electromagnetic energy can couple into the antenna even in the absence of a direct line-of-sight path (fields can diffract, wrap around shielding edges, or penetrate narrow slots). #### 5.1.2 Routing Guidelines Once component placement is complete, begin routing the RF traces. Each RF trace can significantly impact system performance and EMC/EMI compliance, so route them with particular care and deliberate thought. The major considerations are detailed in the following section. **5.1.2.1 Impedance Control** In Section 2.1, we recommend that you commence communications with your PCB manufacturer early in the design process to establish the required PCB routing rules. In Section 4.1.1, we recommend that you designate RF nets as 50 Ω in your schematic design tool. Now that you are routing the PCB traces, we trust you have heard back from your manufacturer. Be sure to apply these routing rules to the 50 Ω characteristic impedance Wi-Fi HaLow signal traces. **5.1.2.2 Bend Angle** Smoothly curved or 45° bends in RF traces are preferred. Sharp corners can introduce discontinuities, so gradual transitions are recommended to support consistent impedance and clean signal propagation. A 45° bend or continuous curve provides a more uniform current path, reducing the chance of localized reflections or unintended radiation. **5.1.2.3 Reference Plane Integrity** Route RF traces exclusively over an uninterrupted ground plane; do not place RF traces over plane splits, gaps, other traces, or isolated copper pours. An unbroken ground plane provides a consistent return path directly beneath the RF trace, which is essential for stable impedance and minimizing unintended radiation. **5.1.2.4 Via Usage and Transitions** RF paths should remain on the outermost copper layer and avoid layer transitions via vias. Routing RF traces entirely on the surface avoids introducing impedance discontinuities and parasitic via inductances. Layer changes inherently degrade signal integrity and are strongly discouraged in RF paths. If an unavoidable mechanical constraint forces a layer change, only then should a single, properly sized via be used, with minimal stub length, and impedance-matched barrel and antipad dimensions. **5.1.2.5 Via Shielding** Coplanar waveguide (CPW) traces should be flanked on both sides by a continuous fence of closely spaced ground vias. This via fencing confines the electromagnetic fields, suppresses parallel-plate modes, and maintains a robust, continuous return path, thereby minimizing undesired coupling and radiation. Vias should be positioned as close as possible to the edge of the CPW ground plane metal; ideally, within 0.5 to 1.0 mm. Denser via spacing improves mode suppression and helps ensure consistent impedance and field confinement along the CPW structure. **5.1.2.6 Thermal Relief and Power-Plane Intersections** For optimal signal integrity, ground vias associated with RF signals should use a solid copper pour rather than thermal relief patterns. This ensures the lowest possible return path impedance and minimizes parasitic effects. However, solid vias can conduct significant heat during soldering, potentially causing assembly challenges or unreliable joints. Thermal reliefs alleviate this risk by limiting heat conduction, but at the expense of RF performance. We recommend retaining a solid ground connection and addressing assembly concerns through process tuning or other local design adjustments. **5.1.2.7 Component Pad Transitions** When transitioning to a wider pad, an abrupt, well-controlled impedance transition is generally preferable, particularly when coordinated with an appropriate ground return (such as removing some ground layers under the pad, if needed). Tapered transitions may look cleaner, but often do not improve impedance matching and can worsen reflections. ![Figure 18: Transition from RF trace to SMA connector](/files/cc84baf31dfb8cf1c64ea50326e69bb6ab576d1f) *Figure 18: Transition from RF trace to SMA connector* ![](/files/73c86117a5e5da6f8989afd2d07faf081647f68b) In the example shown in Figure 18, the RF feedline is designed for a 50 Ω characteristic impedance, referenced to an internal ground plane. However, the RF connector pad is significantly wider than the feedline. To maintain the 50 Ω impedance at this interface, the internal ground layers beneath the pad are removed, shifting the reference plane to the bottom layer. On the left, an abrupt transition is shown in which the trace width and ground reference shift simultaneously, preserving a consistent 50 Ω impedance across the transition. On the right, a tapered trace is used instead. As the trace widens while still referenced to the internal plane, the impedance gradually drops below 50 Ω before returning to that value once the bottom-layer ground plane takes over at the pad. This non-uniform impedance can introduce reflections and degrade RF performance. The best results are achieved by avoiding unnecessary trace width discontinuities altogether. Selecting components, such as 0402 passives, and connectors whose pad dimensions are as close as possible to the desired trace width is recommended. However, the trace width is also typically constrained by the need to mate with the device's interface geometry (e.g., the required pad or bump size), which may impose a minimum trace thickness. In practice, the thinnest component pad width often determines the trace width, which in turn defines the PCB stackup and transmission line type (e.g., CPW or microstrip). Transitions to larger connector geometries (such as SMA or U.FL) can introduce impedance discontinuities due to pad sizes that differ from the RF trace width. These transitions should ideally be measured using a vector network analyzer to verify return loss and ensure acceptable matching. While a full 3D electromagnetic simulation is not mandatory, it can be a valuable tool for predicting performance and reducing the number of layout iterations needed to optimize RF performance. ### 5.2 Universal Serial Bus With data rates up to 480 Mbps, USB signals are 240 MHz radio-frequency signals and should be treated as such. As a digital signal protocol, signal losses can be mitigated or recovered, making signal loss less critical (compared to an RF antenna trace), but the differential-signal nature means that length matching becomes an important consideration. USB signals must be routed according to the length-matching and impedance-control rules defined in Section 4.3. For USB-C, abrupt transitions in the CC signal traces (including using vias) should be avoided wherever possible. Any imperfections in these signal traces can cause reflections to the host controller, which may incorrectly interpret the discontinuity as indicating no peripheral device is connected. ### 5.3 Decoupling After the RF traces, the next most important consideration is the bypass capacitors. Standard best-practice principles apply, as discussed in the following section. Figure 19 illustrates a typical layout. ![Figure 19: Decoupling capacitor placement](/files/dd085ff7a7f90e77edd30f365913d5681e3e9f4b) *Figure 19: Decoupling capacitor placement* #### 5.3.1 Placement Guidelines Decoupling capacitors are most effective when placed to minimize loop area between the capacitor and its associated supply pin. All capacitors should be located as close as practical to their associated pins or supply nodes. When multiple capacitors are placed in parallel on the same pin (for example, a 100 nF capacitor alongside a 4.7 µF capacitor), it may be acceptable to place them side by side or stack them vertically (i.e., on opposite sides of the PCB with a via connection). What matters most is minimizing the inductance of the conductance path and ensuring both capacitors return to a solid ground plane. For designs with long or resistive VDD supply paths, placing sufficient bulk capacitance close to the device is especially important to ensure that transient current demands are met locally. #### 5.3.2 Routing Guidelines Use short, wide copper traces for both power and ground. A ground via should be placed as close as practical to the capacitor ground terminal to connect directly to a continuous ground plane located on the layer below the chip. This ground plane must be unbroken within the area enclosed by the module's outermost grounding vias and decoupling capacitors to provide a well-defined, low-impedance current-return path. ### 5.4 Power Supply With the decoupling capacitors in place, it is now time to turn our attention to the rest of the power supply architecture. #### 5.4.1 Placement Guidelines Placement should aim to minimize both power-supply noise and series resistance. Any noise on the power supplies may be coupled into the RF section of the design and then radiated out of the antenna. This can impact receive sensitivity and also cause the device to fail certification testing. **5.4.1.1 Equivalent Series Resistance** Equivalent series resistance (ESR) may be reduced by placing the power supply, particularly a low-dropout regulator (LDO), close to the VDD pin. **5.4.1.2 Separating Noisy Sources from Sensitive Circuitry** If using a switch-mode power supply, place it as far from the HaLow module as practical. This applies broadly to any circuitry generating high-frequency currents through inductors or ground paths. If ESR in the main supply path is a concern, providing a Kelvin connection to the voltage feedback pin can help mitigate voltage drops. #### 5.4.2 Routing Guidelines The routing of power supply traces directly influences voltage stability, noise coupling, and the effectiveness of decoupling under dynamic loads. The major considerations are detailed in the following section. **5.4.2.1 Star Topology Distribution** Keep all common-mode impedance to a minimum. Power distribution should avoid daisy-chaining and instead use a star-point or short branch to deliver equal-quality supply to each load. This is required for VDD, VDD\_TX, and VDD\_USB, which serve distinct functional domains and must be routed independently from a shared node. Each branch must include its own local decoupling network placed close to the associated power pin. The physical layout should favor short, direct traces from the star point to each load. First, route traces to the capacitor pads, and then to the device pin. **5.4.2.2 Trace Width and Thickness** Power supply traces should be designed for both low resistance and low inductive impedance to support fast current transients without significant voltage droop. The maximum recommended series resistance on the VDD current path is 50 mΩ. The PCB layout should ensure that this limit is not exceeded, accounting for the resistance of the copper traces and any series components in the power path. Using wider copper traces (or better yet, polygon pours) minimizes voltage drop due to DC resistance and reduces inductive impedance at higher frequencies. This becomes especially important during events such as RF transmission or wake-from-sleep transitions, where dynamic current demand can rise sharply. The supply voltage drop between the regulator and the load should remain below 50 mV under peak-current conditions. Avoid routing supply traces through narrow necks, unnecessary detours, or shared segments that may introduce excess impedance or coupling into other supply domains. Avoid overlapping power traces on adjacent layers, which can create capacitive coupling between supplies. **5.4.2.3 Via Usage** Each via contributes its own resistance and inductance, so distributing current across several vias helps maintain power integrity even during fast load steps. This is particularly important for VDD and VDD\_TX. ### 5.5 SDIO / SPI / JTAG Placement and routing should minimize crosstalk and signal integrity issues across these digital interfaces. It is important to address this carefully during layout, as digital signals may appear functional despite poor integrity, which can lead to intermittent or hard-to-diagnose failures later in development or in the field. The following recommendations help maintain clean digital signaling. #### 5.5.1 Placement Guidelines Wherever possible, arrange subsystems on the PCB to enable direct, uncluttered routing of the SDIO/SPI signals, minimizing crossings with other traces or with themselves. Maintain separation between these signal domains to reduce coupling and simplify layout. #### 5.5.2 Routing Guidelines The SDIO and SPI signals should ideally be routed as 50 Ω coplanar waveguides (on outer layers) or as striplines (on internal layers). To preserve signal integrity, keep trace lengths under 50 mm and match them within ±10  mm. Since these are digital signals, resistive and dielectric losses are not a key concern, so the minimum trace width and dielectric type are not critical. These interfaces operate at tens of megahertz, so tight impedance control is not necessary; however, using a standard PCB calculator to size traces for a nominal 50 Ω impedance is still recommended. Coordination with the PCB fabricator for precise impedance control on these traces is not mandatory. SDIO is a point-to-point protocol and should always be routed directly between the host and the peripheral, with no branches in the signal path. When supporting multiple host devices through different builds (for example, by selectively populating 0 Ω resistors), the stub leading to the unused path should be kept as short as possible to maintain signal integrity. For shared buses, arranging devices in a daisy chain helps minimize reflections and ensures the last device sees the best signal. Note that intermediate devices inevitably see stubs from the onward connections. ### 5.6 GPIO GPIO signals have lower priority than other types, so they are typically routed last, using whatever space remains after higher-priority traces are placed. Ensure their routing doesn’t violate existing layout constraints, for example, avoid cutting ground planes beneath RF traces or disrupting return current loops. GPIOs are general-purpose; their function is defined by special firmware builds and Morse Micro board configuration files (BCFs). If tied to a specific application note, any unique signal requirements will be detailed in that note. Electrically, a GPIO driven on one end is effectively grounded at the driver but floating (high impedance) at the load. From the standpoint of nearby RF traces, it resembles an unterminated length of copper that can easily pick up or reradiate signals. If the trace is long or closely spaced to RF, it can act like a stray antenna. Adding 100 pF capacitors to ground can suppress these effects without impacting low-speed digital performance. For GPIO signals that control external RF front-end devices such as RF switches, front-end modules (FEMs), low-noise amplifiers (LNAs), and power amplifiers (PAs), ensure that 100 pF termination capacitors are placed at the RF front-end device control input pins. These capacitors filter out digital power-supply domain noise and prevent it from coupling into the RF front-end signal path. If GPIO traces need to cross adjacent layers or power traces, ensure they do so at right angles to minimize coupling. GPIO traces should only run directly alongside other traces if those signals are tolerant of digital noise, or if GPIO transitions are guaranteed to occur at times that coupling is not consequential. ### 5.7 Diagnostic Ports Placement and routing of the diagnostics connector should ensure a reliable mechanical fit, allow unobstructed cable access, and maintain a clean integration into the PCB stack-up without compromising nearby traces or ground integrity. Place the diagnostics connector with enough clearance for cables or probes to attach and detach freely, and avoid positions that force sharp cable bends. ### 5.8 Protection Placement and routing of protection components must ensure effective suppression of electrostatic discharge, electromagnetic interference, and conducted noise without compromising impedance control or power delivery. #### 5.8.1 Placement Guidelines Electrostatic discharge protection (ESD) components must be placed to intercept disturbances before they propagate into sensitive areas of the design. ESD protection circuitry should be located at the outermost interface with the external environment, close to connectors or antenna feeds, to ensure transients are quickly shunted through short, direct paths to ground. As signals transition between noisy and quiet domains, chokes and filters confine conducted noise, preserving the integrity of downstream circuits. On impedance-sensitive traces, particularly RF paths, any protection must be positioned to minimize parasitic effects and maintain controlled impedance without introducing discontinuities. Similarly, on power nets, protection layout must accommodate wide copper traces to keep ESR low, preventing voltage drops and avoiding inductive artifacts that could degrade supply stability. #### 5.8.2 Routing Guidelines Route to protection devices with the shortest possible traces to minimize series impedance. Avoid tight corners or via transitions that introduce additional parasitics, particularly on RF or high-current power nets. Ensure ground returns are direct and connect to a solid plane to support effective discharge and filtering. ### 5.9 Grounding Ground layout directly impacts power integrity, electromagnetic interference performance, and RF behavior. The following section describes layout techniques and grounding practices necessary to ensure stable operation. Many of the recommendations are repeated, but they have been kept together here so that this section may act as a final checklist on grounding integrity before the board is sent for manufacture. #### 5.9.1 Solid Ground Plane Dedicate at least one layer (typically an inner layer) as a continuous ground plane. Avoid cutting or slotting the ground plane near critical components or between supply and decoupling points. Keep the ground plane unbroken under the MM8108-MF15457, the associated decoupling capacitors, and the RF trace. If signals must transition between layers, note that several adjacent vias will split the ground plane and must be spaced to prevent this. A single, unified ground plane should be maintained throughout. Do not segment or isolate analog and digital grounds within the module footprint. #### 5.9.2 Ground Via Stitching Use generous ground via stitching to connect all ground regions and layers. Every decoupling capacitor should have at least one ground via placed directly at the capacitor pad. Where possible, via-in-pad is preferred. Ground vias should be densely placed around exposed thermal pads, along the chip periphery, and beneath high-current return paths, such as the buck regulator or RF output. Add ground vias at every ground pad for every grounded component. For RF nets, use a direct connection (not a thermal relief). In systems operating in the 850 MHz to 950 MHz band, the wavelength in FR4 is approximately 150 mm. To effectively confine return currents and suppress cavity resonances, stitching vias should be placed at intervals of at least 15 mm (about λ/10). However, to improve margins and further minimize the risk of electromagnetic interference, a tighter pitch of 6 mm or less (approximately λ/25) is recommended. Along critical signals (such as RF or high-speed traces), vias should be spaced no more than 1.0 mm apart (center-to-center). Recommended dimensions include a minimum drill size of 0.3 mm and a pad diameter of at least 0.6 mm, with annular rings meeting fabrication requirements. Place stitching vias every 3.0 mm along plane boundaries and within 1.0 mm of any cutout or slot. #### 5.9.3 Return-Path Control All high-speed or RF signal traces must have a direct return path on the adjacent ground layer. The return current should remain closely coupled beneath the signal trace. Traces must not cross plane splits. ## 6 Application Examples The following examples are intended to capture the basic usage across the three most common host types: PC (USB dongle), embedded Linux (Raspberry Pi), and ARM-based microcontroller (EKH05). ### 6.1 USB Dongle Application Example The following example is a minimal implementation of the MM8108-MF15457 as a USB Wi-Fi HaLow dongle. This is the most straightforward application example we provide (i.e., the one with the fewest components). #### 6.1.1 Bill of Materials The following table lists the components required to implement a Wi-Fi HaLow USB dongle. | | | | | | | ----------- | ------ | --------------------------- | -------------------- | -------- | | Designator | Value | Manufacturer | Part Number | Quantity | | H2 | USBA | Global Connector Technology | USB1061-GF-L-A | 1 | | D1, D5 | Green | SunLED | XZVGR68W-3 | 2 | | D6 | | STMicroelectronics | ESDALC6V1-1U2 | 1 | | D2, D3 | | LittelFuse | SP3522-01ETG | 2 | | D4 | Red | SunLED | XZMDK68W-2 | 1 | | C1 | 2.2 uF | Murata | GRM155R61E225ME15D | 1 | | C2, C4, C6 | 10 uF | Samsung | CL05A106MP5NUNC | 3 | | C5 | 22 pF | TDK | CGA2B2NP01H220J050BA | 1 | | R2 | 453 kΩ | Vishay | CRCW0402453KFKEDC | 1 | | R7 | 220 kΩ | Yageo | RC0201FR-07220KL | 1 | | C3, C8 | 10 uF | Murata | GRM188R61E106MA73J | 2 | | C7 | 100 nF | KEMET | C0402C104K8RACTU | 1 | | H1 | | Bel Cinch | 142-0761-861 | 1 | | L1 | 2.2 uH | Murata | LQM21PN2R2MGHL | 1 | | R1, R3 | 100 kΩ | Yageo | RC0402FR-07100KL | 2 | | R4, R5, R13 | 330 Ω | Yageo | RC0201FR-07330RL | 3 | | U1 | | Morse Micro | MM8108-MF15457 | 1 | | U2 | | Diodes Inc. | AP3401DNTR-G1 | 1 | **Table 5: Bill of Materials for USB Dongle Application** #### 6.1.2 Reference Schematic The schematic is provided in four parts: the MM8108-MF15457, the required decoupling capacitors, the RF connector, and the reset circuitry. ![Figure 20: USB Dongle Application Example: Schematic of MM8108-MF15457](/files/ba9f08fb970f01a4cfa8357e23bb8078e8329b49) *Figure 20: USB Dongle Application Example: Schematic of MM8108-MF15457* The power supply is taken directly from the 5 V USB VBUS line, and a switch-mode power supply is used to minimize waste heat. ![Figure 21: USB Dongle Application Example: Layout of power supply section](/files/20fd56e119b3a170ef0dce65c1567761ca4f7c0e) *Figure 21: USB Dongle Application Example: Layout of power supply section* Some basic indicator LEDs are provided, along with an (optional) push button for WAKE functionality. ![Figure 22: USB Dongle Application Example: Layout of the IO section](/files/fa02a08cae4140af0c87674b262e3a286056a96f) *Figure 22: USB Dongle Application Example: Layout of the IO section* #### 6.1.3 Reference Layout The complete PCB is shown below, where the layout of the RF, USB, decoupling, and IO (LED) traces is clearly visible. The power supply and button are not shown; they appear on the underside of the PCB. ![Figure 23: USB Dongle Application PCB Layout](/files/aa6ec497088c88acdfe482058d73b01e00226907) *Figure 23: USB Dongle Application PCB Layout* #### 6.1.4 Additional Resources Complete details for this application example can be found at [www.morsemicro.com](https://www.google.com/url?q=http://www.morsemicro.com\&sa=D\&source=editors\&ust=1783314268592805\&usg=AOvVaw0jy21yMlDdaZqANlKuLrbR) by searching for the [RD09](https://www.google.com/url?q=https://www.morsemicro.com/resources/design_packages/reference_designs/RD09_v4.1.zip\&sa=D\&source=editors\&ust=1783314268592962\&usg=AOvVaw1wjjUK6I75Cl2gBuUJln1v) reference design. ### 6.2 STM32 Microcontroller Application Example Complete details for an ARM microcontroller-based example can be found at [www.morsemicro.com](https://www.google.com/url?q=http://www.morsemicro.com\&sa=D\&source=editors\&ust=1783314268593257\&usg=AOvVaw2mW7MIB0KIuX8KhwN_1Npu) and searching for the [MM8108-EKH05](https://www.google.com/url?q=https://www.morsemicro.com/resources/design_packages/carrier_boards/MM8108-EKH05_v2.1.zip\&sa=D\&source=editors\&ust=1783314268593377\&usg=AOvVaw01TpmUp6yhp-yNyL3N19l8) evaluation kit. ### 6.3 Raspberry Pi Application Example Complete details for an embedded Linux-based example can be found at [www.morsemicro.com](https://www.google.com/url?q=http://www.morsemicro.com\&sa=D\&source=editors\&ust=1783314268593653\&usg=AOvVaw0uyr8Malt85uPmr_1jFTBn) and searching for the [MMECH17](https://www.google.com/url?q=https://www.morsemicro.com/resources/design_packages/carrier_boards/MMECH17_v3.zip\&sa=D\&source=editors\&ust=1783314268593771\&usg=AOvVaw29HujJ5RKFYMXCogZvG5Nz) application example. ## 7 Design-In Checklist This checklist is intended for hardware designers integrating the MM8108-MF15457 Wi-Fi HaLow module into a new design. It defines key items to verify during schematic capture and PCB layout. Refer to the reference designs (Section 6) for complete schematics and PCB layouts across supported host interfaces ### 7.1 Schematic Checklist #### 7.1.1 RF * Including a pi or tee network on the RF path provides the option for additional filtering. * IF the RF path is exposed to the external environment, AND more protection than the in-built 1 kV is required, THEN include an RF-rated ESD diode at the connector pin. * IF maximizing range is paramount, be mindful that everything you put on the main RF signal path (including the above) degrades the signal quality. ![Figure 24: RF Schematic](/files/f236c7eaae2ccda215a74f00069893b76ae6bcc9) *Figure 24: RF Schematic* #### 7.1.2 Power Supply * Ensure the module power supply (LDO or SMPS) supports at least 500 mA of current. * Minimum of 10 uF of capacitance on VDD, VDD\_TX, and VDD\_USB. * An additional 100 nF capacitor on VDD, VDD\_TX, and VDD\_USB is recommended. * Minimum of 100 nF of capacitance on VDDIO. ![Figure 25: Module decoupling capacitors](/files/de6124af143cb592651ffc595bd5bafd26043c28) *Figure 25: Module decoupling capacitors* #### 7.1.3 Host Interface The MM8108-MF15457 has multiple methods of operation with a host device. Follow the sub-section corresponding to the intended host interface (SDIO, SPI, or USB). **7.1.3.1 SDIO** * Place pull-up resistors (10 to 100 kΩ) on SDIO\_CMD, SDIO\_D0, SDIO\_D1, SDIO\_D2, and SDIO\_D3. * Connect the SDIO pull-up resistors to the VDDIO power rail. * Ensure no pull-up resistor is present on SDIO\_CLK. * (Optional) Provision series-damping resistors on all SDIO lines for signal-integrity tuning. Populate as 0 Ω by default, and substitute with values in the 10 to 100 Ω range if ringing, overshoot, or EMI issues are observed. * Notes on USB: * USB D+/D− can be left unconnected when SDIO is the primary transport. * You must connect VDD\_USB to the VDD power rail even if USB is not used. ![Figure 26: SDIO Schematic](/files/3ea724fa887392c8633464bbe154a1dc3637a0f7) *Figure 26: SDIO Schematic* **7.1.3.2 SPI** * Place a pull-up resistor (10 to100 kΩ) on SDIO\_D2 only (required for SPI operation). * Connect the SDIO\_D2 pull-up resistor to the VDDIO power rail. * (Optional) Provision series-damping resistors on all SPI lines for signal-integrity tuning. Populate 0 Ω resistors by default, and substitute with values in the 10 to 100 Ω range if ringing, overshoot, or EMI issues are observed. * Notes on USB: * USB D+/D− can be left unconnected when SPI is the primary transport. * You must connect VDD\_USB to the VDD power rail even if USB is not used. ![Figure 27: SPI Schematic](/files/6bce28adc84d22848feb870a92c8506057c040c8) *Figure 27: SPI Schematic* **7.1.3.3 USB** * ESD protection on USB data lines (D+ and D−) must be specifically designed for USB 2.0 operation (e.g., [SP3401-02UTG](https://www.google.com/url?q=https://www.littelfuse.com/products/overvoltage-protection/tvs-diode-arrays/low-ultra-low-capacitance/sp3401/sp3401-02utg\&sa=D\&source=editors\&ust=1783314268599356\&usg=AOvVaw01oezau_tkLJhqjpXUOxm0)). * Note: SDIO/SPI traces can be left unconnected when USB is the primary transport. ![Figure 28: USB Schematic](/files/7b77996e4c00672c47ad1c11422aee9e8281d187) *Figure 28: USB Schematic* #### 7.1.4 JTAG * (Optional) Connect JTAG signals to test points. * Ensure no pull-down resistors are present on JTAG lines. ![Figure 29: JTAG Schematic](/files/e5ead0f89fe94dfd6fdd5e4d7399e70418c34126) *Figure 29: JTAG Schematic* #### 7.1.5 GPIO * Connect the GPIOs according to the defined pin mapping, as shown below. * If power save mode is used, connect BUSY (GPIO2 on pin 29) directly to a host input GPIO. * Ensure all unused GPIOs are left unconnected. * (Optional) Connect GPIO0 to a test point. ![Figure 30: GPIO Schematic](/files/c0e58d3cd9d40c5919d8fbb2bbb0392491cf7068) *Figure 30: GPIO Schematic* #### 7.1.6 Wake * IF power saving mode is required, THEN connect the WAKE pin to a host output GPIO. * IF power saving mode is not required, THEN leave the WAKE pin unconnected. #### 7.1.7 Reset * Connect RESET\_N to a host output GPIO. * Include an RC network on RESET\_N with 220 kΩ pull-up and 2.2 µF capacitor to ground. ![Figure 31: Wake and Reset Schematic](/files/96de3ba3b6c5695353ce6195b3c0326d94e906b6) *Figure 31: Wake and Reset Schematic* ### 7.2 PCB Layout Checklist #### 7.2.1 RF * Ensure RF trace impedance is 50 Ω ±10%. * Avoid RF trace right-angle bends. * Minimize RF trace length. * Surround the RF trace with ground stitching vias. * Avoid significant PCB trace width changes through matching components and antenna pads. * Place the RF ESD diode as close as possible to the antenna connector. #### 7.2.2 Power Supply * Place decoupling capacitors as close as possible to the module power supply pins. * Place smaller value capacitors closer to the pin, followed by larger capacitors. * Ensure power traces support at least 1A of (instantaneous) current. * Use multiple vias when transitioning power traces between PCB layers. #### 7.2.3 SDIO/SPI * Ensure SDIO/SPI lines are length matched to ±10 mm. * Controlling SDIO/SPI trace impedance to 50 Ω is recommended. * Ensure no stubs are present on SDIO/SPI signals. #### 7.2.4 USB * Ensure USB data lines are routed as 90 Ω differential pairs. * Ensure USB data lines are length-matched with ≤100 ps skew (within 1 mm recommended). * Ensure compliance with USB 2.0 requirements. ## 8 Revision History | | | | | -------------- | ------------ | ------------------------------------------------------- | | Release Number | Release Date | Release Notes | | Version 2 | 20 June 2026 | Added note on level shifter. Added Design-In checklist. | | Version 1 | 22 Oct 2025 | Initial release | Morse Micro provides this information "as is" without warranties of any kind, express or implied. No guarantee is made as to the accuracy, completeness, or suitability of this information or Morse Micro’s products for any specific purpose. Use of this information and products is at the user’s sole risk. Morse Micro products are not designed or tested for use in mission-critical systems, and should not be used in such applications. Performance specifications are based on internal testing and are believed to be reliable; however, they are not guaranteed. It is the Buyer’s responsibility to test and validate all product performance, compatibility, and compliance, both in isolation and within end applications. Morse Micro assumes no liability for the use or application of any product, circuit, or information described herein. No license or other rights—express or implied—are granted under Morse Micro’s intellectual property. This document contains proprietary information of Morse Micro and is subject to change without notice. Wi-Fi®, Wi-Fi HaLow™, and the Wi-Fi logo are trademarks of Wi-Fi Alliance. ZigBee™ and Z-Wave™ are trademarks of their respective owners. All other trademarks are the property of their respective owners. [\[a\]](#cmnt_ref1)Just a note for the next release of this document. We've update the schematic sheet symbol of this part as the current symbol required connecting a trace to the NC pin which doesn't really make sense. (It won't let me paste the new symbol). Check Altium for latest.